Alinx AXKU040 - Part 9: Gigabit Ethernet Interface

KINTEX UltraScale+ FPGA Board AXKU040 User Manual
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Part 9: Gigabit Ethernet Interface
There are 2 Gigabit Ethernet ports on the AXKU040 FPGA Development
board. The GPHY chip uses Micrel's KSZ9031RNX Ethernet PHY chip to
provide users with network communication services. The KSZ9031RNX chip
supports 10/100/1000 Mbps network transmission rate, and communicates
with the MAC layer of the system through the RGMII interface. KSZ9031RNX
supports MDI/MDX adaptation, various speed adaptation, Master/Slave
adaptation, and supports MDIO bus for PHY register management.
When the KSZ9031RNX is powered on, it will detect the level status of
some specific IOs to determine its own operating mode. Table 3-5-1 describes
the default settings after the GPHY chip is powered on.
Configuration Pin
Instructions
Configuration value
PHYAD[2:0]
MDIO/MDC Mode PHY Address
PHY Address 011
CLK125_EN
Enable 125Mhz clock output selection
Enable
LED_MODE
LED light mode configuration
Single LED light mode
MODE0~MODE3
Link adaptation and full duplex
configuration
10/100/1000 adaptive, compatible
with full-duplex, half-duplex
Table 9-1: PHY chip default configuration value
When the network is connected to Gigabit Ethernet, the data transmission
of FPGA chip and PHY chip KSZ9031RNX is communicated through the RGMII
bus, the transmission clock is 125Mhz, and the data is sampled on the rising
edge and falling samples of the clock.
When the network is connected to 100M Ethernet, the data transmission of
FPGA chip and PHY chip KSZ9031RNX is communicated through RMII bus,
and the transmission clock is 25Mhz. Data is sampled on the rising edge and
falling samples of the clock.