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Alinx AXKU040 - Part 12: SMA and SATA Interface

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KINTEX UltraScale+ FPGA Board AXKU040 User Manual
49 / 59
www.alinx.com
Part 12: SMA and SATA Interface
The AXKU040 FPGA development board is designed with 6 SMA
interfaces, which are connected to the BANK225 high-speed transceiver ,
including a pair of TX, a pair of RX, and a pair of clock signals. Provide
customers with high-speed external interfaces. In addition, two SATA ports are
reserved on the FPGA board for connecting solid state drives.
The schematic diagram of FPGA and SMA interface connection is shown
in Figure 12-1.
Figure 12-1: SMA Connection Schematic
SMA Interface pin assignment:
Signal Name
FPGA Pin
FPGA Pin
Number
Description
SMA_CLKP
MGTREFCLK1P_225
Y6
Transceiver Clock Signal
SMA_CLKN
MGTREFCLK1N_225
Y5
Transceiver Clock Signal
SMA_TX_P
MGTHTXP3_225
AC4
Transceiver Signal Output
SMA_TX_N
MGTHTXN3_225
AC3
Transceiver Signal Output
SMA_RX_P
MGTHRXP3_225
AB2
Transceiver Signal Input

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