Alinx AXKU040 - Page 25

KINTEX UltraScale+ FPGA Board AXKU040 User Manual
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Figure 9-1: FPGA Chip and GPHY connection diagram
The 1
st
Gigabit Ethernet interface pin assignments are as follows:
Signal Name
Pin Name
Pin
Number
Description
PHY1_GTXC
IO_L4N_T0U_N7_DBC_AD7N_66
A10
Ethernet 1 Transmit Clock
PHY1_TXD0
IO_L14N_T2L_N3_GC_66
G12
Ethernet 1 Transmit Data bit0
PHY1_TXD1
IO_L2P_T0L_N2_66
B9
Ethernet 1 Transmit Data bit1
PHY1_TXD2
IO_L2N_T0L_N3_66
A9
Ethernet 1 Transmit Data bit2
PHY1_TXD3
IO_L4P_T0U_N6_DBC_AD7P_66
B10
Ethernet 1 Transmit Data bit3
PHY1_TXEN
IO_L21N_T3L_N5_AD8N_66
B11
Ethernet 1 Transmit Enable
Signal
PHY1_RXC
IO_L14P_T2L_N2_GC_66
H12
Ethernet 1 Receive Clock
PHY1_RXD0
IO_L23P_T3U_N8_66
A13
Ethernet 1 Receive Data Bit0
PHY1_RXD1
IO_L20N_T3L_N3_AD1N_66
B12
Ethernet 1 Receive Data Bit1
PHY1_RXD2
IO_L23N_T3U_N9_66
A12
Ethernet 1 Receive Data Bit2
PHY1_RXD3
IO_L21P_T3L_N4_AD8P_66
C11
Ethernet 1 Receive Data Bit3
PHY1_RXDV
IO_L20P_T3L_N2_AD1P_66
C12
Ethernet 1 Receive Data Enable
Signal
PHY1_MDC
IO_T2U_N12_66
F12
Ethernet 1 MDIO Management
Clock
PHY1_MDIO
IO_T3U_N12_66
E12
Ethernet 1 MDIO Management
Data
PHY1_RESET
IO_T1U_N12_66
L9
Ethernet Chip Reset