Alinx AXKU040 - Page 26

KINTEX UltraScale+ FPGA Board AXKU040 User Manual
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The 2
nd
Gigabit Ethernet interface pin assignments are as follows:
Signal Name
Pin Name
Pin
Number
Description
PHY2_GTXC
IO_L10P_T1U_N6_QBC_AD4P
_67
B24
Ethernet 2 Transmit Clock
PHY2_TXD0
IO_L17P_T2U_N8_AD10P_67
B20
Ethernet 2 Transmit Data bit0
PHY2_TXD1
IO_L17N_T2U_N9_AD10N_67
A20
Ethernet 2 Transmit Data bit1
PHY2_TXD2
IO_L15P_T2L_N4_AD11P_67
B21
Ethernet 2 Transmit Data bit2
PHY2_TXD3
IO_L15N_T2L_N5_AD11N_67
B22
Ethernet 2 Transmit Data bit3
PHY2_TXEN
IO_L10N_T1U_N7_QBC_AD4N
_67
A24
Ethernet 2 Transmit Enable Signal
PHY2_RXC
IO_L13P_T2L_N0_GC_QBC_6
7
D23
Ethernet 2 Receive Clock
PHY2_RXD0
IO_L4P_T0U_N6_DBC_AD7P_
67
B29
Ethernet 2 Receive Data Bit0
PHY2_RXD1
IO_L6N_T0U_N11_AD6N_67
A28
Ethernet 2 Receive Data Bit1
PHY2_RXD2
IO_L6P_T0U_N10_AD6P_67
A27
Ethernet 2 Receive Data Bit2
PHY2_RXD3
IO_L13N_T2L_N1_GC_QBC_6
7
C23
Ethernet 2 Receive Data Bit3
PHY2_RXDV
IO_L4N_T0U_N7_DBC_AD7N_
67
A29
Ethernet 2 Receive Data Enable Signal
PHY2_MDC
IO_T1U_N12_67
A23
Ethernet 2 MDIO Management
Clock
PHY2_MDIO
IO_T2U_N12_67
A22
Ethernet 2 MDIO Management Data
PHY2_RESET
IO_T3U_N12_67
H22
Ethernet Chip Reset