Timer and Counter Instructions
Chapter 5
57
Figure 5.5
Retentive
T
imer with Retentive T
imer Reset T
iming Diagram
TRUE
FALSE
ÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉ
ON
OFF
0123456789101112
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
1
2
0
4
5
6
3
7
8
9
ON
OFF
ON
OFF
Time
in Seconds
When Reset Switch is Closed,
T
imed Bit is Reset. Accumulated
V
alue is Reset and Held at Zero
Until Reset Switch is Opened.
Input Switch 1
13/06
Enable Bit 052/17
Preset V
alue
ACC Value Retained When
Rung Condition Goes False
Accumulated V
alue
T
imed Bit 052/15
Output Lamp 01
1/04
Rung 1 - Retentive
T
imer Preset for
9 Sec. Delay
Rung 2 - T
imer T
urns On
Bit 010/04 When T
imes Out
||
06
( R
TO )
1.0
113 052
||
15
()
04
052 010
PR 009
AC 009
Input Switch
T
imed Bit
Output Lamp
AC = PR
ON
OFF
Reset Switch 1
13/07
Rung 3 - Resets the
Retentive T
imer
||
07
( R
TR )
113 052
Reset Switch
PR 009
AC 009
Enable
Bit is
Reset
When
Input
Switch is
Opened.
ÉÉ
ÉÉÉÉÉÉÉ
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