Alstom MiCOM P546 - Page 188

P54x/EN OP/La4 Operation
(OP) 5-14 MiCOM P543, P544, P545 & P546
OP
The characteristic is determined by four protection settings:
s1 The basic differential current setting which determines the minimum pick-up level of
the relay.
k1 The lower percentage bias setting used when the bias current is below
s2. This
provides stability for small CT mismatches, whilst ensuring good sensitivity to
resistive faults under heavy load conditions.
s2 A bias current threshold setting, above which the higher percentage bias k2 is
used.
k2 The higher percentage bias setting used to improve relay stability under heavy
through fault current conditions.
The tripping criteria can be formulated as:
1. For |
bias| < s2,
|diff| > k1.| bias| + s1
2. For |
bias| > s2,
|diff| > k2.| bias| - (k2 - k1). s2 + s1
When a trip is issued by the differential element, in addition to tripping the local breaker, the
relay will send a differential intertrip signal to the remote terminals. This will ensure tripping
of all ends of the protected line, even for marginal fault conditions.
The differential protection can be time delayed using either a definite or inverse time
characteristic.
The d High Set element is an unrestrained element designed to provide high speed
operation in the event of CT saturation. Where transformer inrush restraint is used, the
resultant second harmonic current produced from CT saturation may cause slow relay
operation. The high set element will be automatically enabled when inrush restraint is
enabled, otherwise it is not operational.
The logic diagram for Differential protection is shown in Figure 2
P1693ENd
&
&
&
A phase Differential comparator
B phase Differential comparator
C phase Differential comparator
DDB Inhibit C Diff (613)
(Remote Relay Inhibit) (From. Remote relay)
DDB Inhibit C Diff (258)
(Local Relay Inhibit)
INTSIG Recieve Diff Intertrip B
INTSIG Recieve Diff Intertrip A
INTSIG Recieve Diff Intertrip C
(From. Remote relay)
(From. Remote relay)
(From. Remote relay)
DDB Diff Start A (738)
DDB Diff Trip A (583)
INTSIG SEND Diff Intertrip A
(To. Remote relay)
DDB Diff Start B (739)
DDB Diff Trip B (584)
INTSIG SEND Diff Intertrip B
(To. Remote relay)
DDB Diff Start C (740)
DDB Diff Trip C (585)
INTSIG SEND Diff Intertrip C
(To. Remote relay)
DDB Diff Intertrip A (587)
DDB Diff Intertrip B (588)
DDB Diff Intertrip C (589)
t
0
(0s~100m)
SET: Phase time delay
SET: Phase time delay
(0s~100s)
SET: Phase time delay
(0s~100s)
t
0
t
0
Figure 2 Differential logic diagram