P54x/EN OP/La4 Operation
(OP) 5-96
MiCOM P543, P544, P545 & P546
OP
INTSIG Current Prot SEF Trip
INTSIG ISEF < Fast Undercurrent
DDB CB1 Fail 1Trip (834)
&
&
&
&
SET: CB Fail 1 Timer
0
0
1
Alarm Breaker
Fail
DDB CB1 Fail 2Trip (835)
SET:
CB Fail 2 Status
Enable
Disable
&
0
1
t
0
&
1
&
1
1
1
&
1
S
R
D
Q
S
Q
S
Q
S
Q
1
1
1
DDB External Trip A (535)
INTSIG Any Trip Phase A
INTSIG IA< Fast Undercurrent CB1
DDB External Trip B (536)
INTSIG IB< Fast Undercurrent CB1
DDB External Trip C (537)
INTSIG IC< Fast Undercurrent CB1
INTSIG Any Trip Phase B
INTSIG Any Trip Phase C
DDB External Trip A (535)
DDB CB1 Open A ph (904)
Setting
Ext Tip Reset
0 I< Only
1 CB Open & I<
2 Prot Reset & I<
S
Q
DDB CB1 External Trip B (536)
DDB CB1 Open B ph (905)
Setting
Ext Tip Reset
0 I< Only
1 CB Open & I<
2 Prot Reset & I<
S
Q
S
Q
1
DDB CB1 External Trip C (537)
DDB CB1 Open C ph (906)
Setting
Ext Tip Reset
0 I< Only
1 CB Open & I<
2 Prot Reset & I<
S
Q
SET: CB Fail 1 Timer
DDB External Trip3ph (534)
DDB CB1 Open 3 ph (903)
SET: CB Fail 1 Timer
Setting
Ext Tip Reset
0 I< Only
1 CB Open & I<
2 Prot Reset & I<
SET: CB Fail 2 Timer - SET CB Fail 1 Timer
t
t
t
P1108ENm
R
D
R
D
R
D
R
D
R
D
R
D
R
D
SET:
CB Fail 2 Status
Enable
Disable
S
Q
Setting
Volt Prot Reset
0 I< Only
1 CB Open & I<
2 Prot Reset & I<
R
D
Any voltage trip
1
DDB All Poles Dead (890)
DDB Aid1 WI Trip3Ph (642)
1
DDB Aid1 WI Trip A (637)
DDB Aid2 WI Trip A (647)
&
DDB Aid1 WI Trip3Ph (652)
&
1
DDB Aid1 WI Trip B (638)
DDB Aid2 WI Trip B (648)
&
1
DDB Aid1 WI Trip C (639)
DDB Aid2 WI Trip C (649)
&
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
WI Prot Reset = Enable
Figure 66 CB1 failure logic for P544 and P546 models