Operation P54x/EN OP/La4
MiCOM P543, P544, P545 & P546
(OP) 5-95
OP
The complete breaker fail logic is illustrated in Figure 65, Figure 66 and Figure 68.
INTSIG Current Prot SEF Trip
INTSIG ISEF < Fast Undercurrent
DDB Bfail 1Trip 3ph (834)
&
&
&
&
SET: CB Fail 1 Timer
0
0
1
Alarm Breaker
Fail
DDB Bfail 2Trip 3ph (835)
SET:
CB Fail 2 Status
Enable
Disable
&
0
1
t
0
&
1
&
1
1
1
&
1
S
Q
1
1
1
DDB External Trip A (535)
INTSIG Any Trip Phase A
INTSIG IA< Fast Undercurrent
DDB External Trip B (536)
INTSIG IB< Fast Undercurrent
DDB External Trip C (537)
INTSIG IC< Fast Undercurrent
INTSIG Any Trip Phase B
INTSIG Any Trip Phase C
DDB External Trip A (535)
DDB Pole Dead A (892)
Setting
Ext Tip Reset
0 I< Only
1 CB Open & I<
2 Prot Reset & I<
S
Q
DDB External Trip B (536)
DDB Pole Dead B (893)
Setting
Ext Tip Reset
0 I< Only
1 CB Open & I<
2 Prot Reset & I<
S
Q
S
Q
1
DDB External Trip C (537)
DDB Pole Dead C (894)
Setting
Ext Tip Reset
0 I< Only
1 CB Open & I<
2 Prot Reset & I<
S
Q
SET: CB Fail 1 Timer
DDB External Trip3ph (534)
DDB All Poles Dead (890)
SET: CB Fail 1 Timer
Setting
Ext Tip Reset
0 I< Only
1 CB Open & I<
2 Prot Reset & I<
SET: CB Fail 2 Timer - SET CB Fail 1 Timer
t
t
t
P1108ENk
R
D
R
D
R
D
R
D
R
D
SET:
CB Fail 2 Status
Enable
Disable
S
Q
Setting
Volt Prot Reset
0 I< Only
1 CB Open & I<
2 Prot Reset & I<
R
D
Any voltage trip
DDB All Poles Dead (890)
2
1
0
2
1
0
2
1
0
2
1
0
2
1
0
S
R
D
Q
S
Q
S
Q
R
D
R
D
1
DDB Aid1 WI Trip A (637)
DDB Aid2 WI Trip A (647)
1
DDB Aid1 WI Trip B (638)
DDB Aid2 WI Trip B (648)
1
DDB Aid1 WI Trip C (639)
DDB Aid2 WI Trip C (649)
1
DDB Aid1 WI Trip3Ph (642)
DDB Aid1 WI Trip3Ph (652)
WI Prot Reset = Enable
&
&
&
&
Figure 65 CB failure for P543 and P545 models