SERVICE MANUAL R5888C
QUADRAMHO Chapter 2
Page 43 of 74
provided. These have a very fast reset time and are connected so as to block
comparator operation when the line is de-energised, as shown in Figure 55.
The actual blocking operation is performed under software control in the scheme
logic module.
The principle of operation of the current level detectors is explained with the help
of Figure 56. If the instantaneous amplitude of the input voltage (VI
N
) exceeds a
threshold setting V
REF
either on a positive half cycle or on an inverted negative half
cycle, a timer t1 is started. If t
1
finishes before the non-inverted or the inverted input
signal has fallen below V
REF
, the input sinewave is known to be greater than the
level detector setting and the output is set high.
At the same time as the output is set, a second timer t
2
is started, whose purpose is
to bridge the time interval between the positive and negative half cycles. So While
t
2
is running, the output cannot reset. When the level V
REF
is exceeded on the next
half cycle, the output is kept in the operated state. Only if the threshold level fails to
be exceeded on the next half cycle, is the output reset after t
2
finishes. The output
also resets if the input signal becomes a unidirectional signal greater than V
REF
,
after both t
1
and t
2
have timed out. Positive feedback is applied from output to
input to give a reset/operate ratio of 0.90 to prevent chatter when the input signal
is at the pick-up level.
The current level detectors are designed to restrict the operative range of the relay,
preventing excessive sensitivity, although because they have a low setting (5% of
rated current at the relay reference setting), this restriction does not constitute any
practical disadvantage. Hence the maximum SIR for ground faults is 131 and for
phase faults is 228. The operating time of the level detector circuit is fast enough
not to limit the minimum operating time of the relay. The maximum reset time of the
level detector is less than the fastest practical comparator operating time.
The current level detector design is such that it can only operate on signals at
around the power system frequency, a characteristic which complements the
operating principle of the comparator. The level detector operation is little affected
by high levels of harmonic, low frequency and exponential contamination of the
power frequency input signal and therefore the input signals can be taken from
before the band pass filters. This eliminates the problems of stored energy slowing
the level detector reset times.
5.9 Inhibition of the comparator
With bus bar VTs, the comparator returns naturally to a restrained condition when
the circuit breaker is opened. However, when line VTs are used the relay must take
special measures to ensure the comparators reset when the line is de-energised.
In addition to the current level detectors, the relay contains voltage level detectors
operating on a similar principle, with a setting of approximately 70% of rated
voltage. If the transmission line is de-energised, the voltage and current level
detectors of the de-energised poles reset, a “pole dead” signal is produced and
after 20ms is supplied to the “inhibit” terminals of the relevant comparators as
shown in Figure 57. This terminal, when activated, causes the counter of the
comparator to register all changes of state of each input A and B as down counts.
The counters of any comparators which have operated, will be rapidly
decremented to zero when the transmission line is de-energised (See also
Figure 34). The implementation of the “pole dead” signals is performed by
software operations in the scheme logic module.
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