SERVICE MANUAL R5888C
QUADRAMHO Chapter 2
Page 16 of 74
4.9.15 Inoperative alarm
The relay inoperative alarm circuit on the scheme logic board monitors a pulse
which is normally present on Port 2 bit 6 of the microcontroller. If the
microcontroller fails to execute the normal scheme loop, the pulse ceases to be
present causing the “Relay Inoperative” alarm to operate. Removal of the pulse is
caused by the following:
a) Failure of the microcontroller.
b) Selection of a non-valid scheme option.
c) Failure of the +5V rail.
d) Operation of VTS with SW3 set to right hand position.
e) Failure of comparator during self test routine.
f) Energisation of the miniature circuit breaker open opto coupler (MCB version
only).
The inoperative alarm circuit also monitors the +12V rails; if this drops below
approximately 7.5V then the Relay Inoperative alarm will be given.
4.9.16 Zone 1 interrupt gating logic
The Zone 1 interrupt gating logic is a hardware gating of the Zone 1 comparator
outputs with the corresponding low set current level detectors (LDLS) and the high
set neutral level detector (LDHSN). This ensures that an interrupt can only take
place when a trip condition occurs on Zone 1.
4.9.17 Synchronised polarising (memory) hardware
The operation of the synchronous polarising (digital memory) is described in
Section 5.2.2.
The basic hardware associated with the memory is as follows. The memory uses
one phase (V
C
) of the input 3 phase volts to the relay. This input is squared and
then level shifted before being input to the microcontroller. Only 1 phase of the
memory output (V
MC
) is produced by the microcontroller, the other two (V
MA
and
V
MB
) are derived from this using external hardware components.
Voltage V
MA
is produced by first shifting V
MC
by –90° and then by a further 30° to
give V
MC
– /120° (V
MA
)
Voltage V
MB
is produced by inverting V
MC
(giving V
MC
–/180° ) and then shifting
by –60° to give V
MC
– /240° (V
MB
).
4.9.18 Indication
The indications of the scheme logic are given by nine LEDs. All these indications
are driven by the scheme logic microcontroller. Eight of the indications are
controlled by PPI 1 port B and are contained on the scheme logic processor board.
The ninth LED is controlled by PPI 2 port B bit 5 and is contained on the opto
isolator board.
All nine indication LEDs are buffered by transistors to enable sufficient current to be
provided for a good level of illumination.
The eight indications of the scheme logic processor board also supply external
outputs which are available on socket 2 on the miniature relay module (see also
Sections 5.16.41 and 5.16.42).
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