SERVICE MANUAL R5888C
QUADRAMHO Chapter 2
Page 5 of 74
The time delay of 26 to 36ms between fault inception and signal transfer is
sufficient to allow fast tripping to occur, if electrical conditions permit, before the
intervention of the filters. If fast tripping does not occur, the 26 to 36ms delay is
long enough for the transient errors of the band pass filters, caused by the
collapsing voltage, to have decayed away before signal transfer to the band pass
outputs.
At the instant of switching in the band pass filters, a step in the voltage waveform
may arise and to ensure that this causes no confusion to the comparators a
momentary inhibit pulse is sent to all the comparators. The voltage supply is
switched back to normal when (a) the fault is removed by a remote breaker so that
the voltage is restored to normal and the voltage level detectors pick up again, (b)
when the fault is cleared by de-energising the line such that one or more pole-dead
level detectors operate. This control logic is performed by software in the scheme
logic module (see Section 5.16.18 and Figure 66).
When the relay trips the circuit breaker, a logic signal is sent from the scheme
logic module to the input labelled “TRIP” to instruct the relay reach to be increased
by 5% by reducing the gain of the voltage buffer amplifiers, which produce outputs
V
A
, V
B
and V
C
, by 5%. This hysterisis control defines the reset ratio of the relay and
prevents chatter of relay output contacts for faults on the boundary of operation
(see Section 5.16.19).
The outputs V
A
, V
B
and V
C
are buffered by operational amplifiers which produce
outputs V
A
', V
B
'
and V
C
' respectively.
The C phase output from the band pass filter is buffered to drive the memory
facility of the relay, see Section 4.9.17, on output V
mem
.
The overall transfer functions for the voltage input module with healthy line
conditions at the nominal power system frequencies are:
Vout
= 0.066304
/–10° (50Hz models)
Vin
Vout
= 0.065854
/–12°
(60Hz models)
Vin
4.3 The current input module RFC 15
This module receives current from the line current transformers on inputs
I
A
, I
B
, I
C
and I
N
via the heavy duty plug bridge piece 1Y on the side of the module and
produces the replica impedance signals
I
A
1
and I
A
2,
I
B
1 and I
B
2,
I
C
1
and I
C
2,
I
N
1,
I
N
2
and I
N
3
(see Block Diagram Figure 7).
Replica impedance signals are generated by the mixing of magnetic fluxes in the
transphasor units, as described in detail in Section 5.14. Each transphasor
arrangement produces an output voltage of 0.34 V/A (1A relay) across a 5kΩ
load located in the phase and neutral module. The residual compensation
arrangement produces an extra output on
I
N
1– I
N
2
of 0.068 V/A (1A relay)
across a 1kΩ load, also located in the phase and neutral module. Each output is
calibrated at the factory by use of the trimpot T.
The replica phase angles are set by switches “
/θPh” and “/θN” on the relay facia
(see Figure 8) which have a setting range of 45° to 85° in 5° steps. These switches
control the variable resistors shown in Figure 7. The angle setting for currents
I
A
, I
B
and I
C
are ganged.
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