SERVICE MANUAL R5888C
QUADRAMHO Chapter 2
Page 17 of 74
4.9.19 Opto isolators
There are three different operating voltages as given in the following table:
Nominal Operative range Absolute max
48/54V 37.5 – 60V 64.8V
110/125V 87.5 – 137.5V 150V
220/250V 175 – 275V 300V
There are five opto isolator inputs available in the scheme logic module; all of
these are fitted on all voltage versions of the board. The opto isolator inputs are
used in the schemes and the functions of these are described in Section 5.16.29.
The opto isolators have a defined minimum operating voltage of greater than 10V
(all voltage versions). Transient suppressors are fitted on the inputs to prevent
damage to the opto isolators. A time delay of between 0.3 and 1.1ms is
incorporated into the output circuit of each opto isolator, this is to prevent transient
operation of the scheme logic inputs. A guard ring (earthed) is used to protect the
output side of the opto isolator from noise that may be present on the input side.
4.9.20 Zero sequence voltage level detector
The zero sequence voltage level detector (LDVO) is used by the VTS to detect an
imbalance in the system voltage. This level detector is designed to operate for a
voltage drop of 45% or greater in any one phase. The level detector is designed to
operate over the frequency range 47 to 61Hz.
The input level of pick up voltage for the frequency range is as follows:
50Hz (47 – 51) P/U = 38 – 52% of rated volts
60Hz (56 – 61) P/U = 40 – 57% of rated volts
A block diagram of the level detector is shown in the main block diagram of the
scheme logic opto board (See Figure 24).
Operation and circuit description
The three phase voltages V
A
', V
B
' & V
C
' are added together to produce the zero
sequence voltage (if all phase voltages are present then this summation will be
zero). This is then passed through an input amplifier and low pass filter. The input
amplifier matches the input signal level to the reference level of the voltage
comparator while the low pass filter is used to reject harmonics. The voltage
comparator detects if the input voltage exceeds the reference level; if this occurs,
the output of the level detector is set high. The voltage comparator uses two
reference levels, one for the positive half cycle and one for the negative half cycle.
Hysteresis is added to ensure no chatter exists on the output which could occur if
the input signal level is on the threshold of operation of the level detector. A drop
off timer (9 – 12ms) is used to hold the output high when the input signal level
drops below the reference level, thus filling in the gaps between the half cycles.
4.9.21 High set current level detectors
The high set phase current level detectors (LDHSA, B & C) are used to improve
stability of operation in the Blocking and Permissive Overreach (with Weak Infeed)
schemes.
The operating principle is identical to the zero sequence voltage level detector
(LDVO). The only difference is that the summing amplifier has been replaced by a
high gain input stage to match the low input signal levels produced by the current
measuring circuitry (see Figure 24) to the level required by the level detector.
To Next Page
Loading...