SERVICE MANUAL R5888C
QUADRAMHO Chapter 2
Page 35 of 74
contains its own logic circuits, counter, constraint timer etc. Figure 34 shows a
flowchart of the sequence comparator logic process.
5.1.3 Exclusion of noise
The following interfacing and preconditioning measures ensure that the full high
speed performance potential of the comparator is achieved even with severely
contaminated relay input signals:
1) Good physical layout and electrical filtering have been used to exclude high
frequency noise generated in the substation. The relay terminals and all of the
relay modules which interface with the outside world are concentrated in the
right hand side of the relay case. The interface modules provide electrical
isolation to 5kV peak, using isolating transformers with screens to shunt high
frequency currents to earth and so attenuate common mode interference.
Transverse mode interference is attenuated by low pass filters. The measuring
and control modules which occupy the left hand side of the relay case, therefore
operate in a quiet electrical environment.
2) Other high frequency signals, such as travelling wave effects and high harmonic
frequencies, are attenuated by low pass filters which cut off at about 120Hz.
3) Exponential components of the current supply are attenuated with a short time
constant (typically less than 1ms) by the main current input devices of the relay,
known as transphasors, described later. In the quadrilateral version of
Quadramho, current transformers are also used, together with band pass filters
to remove exponential components.
4) Coupling capacitor voltage transformer (CVT) transients are prevented from
having any effect on the polarising signal by the dominant effect of sound
phase or synchronous polarising, described later. Switched band pass filters are
used to eliminate excessive effects of CVT transients in other relay signals
derived from the voltage supply.
5.1.4 Phase shifting circuit
To develop impedance characteristics such as the mho, the phase comparator
needs its polarising quantity to be phase shifted by a lagging angle (See Figure
35). Because the comparator operates at high speed the design avoids energy
storing phase shift circuits, for instance capacitor-resistor networks, which have
poor transient response. As the comparator deals with square waves which can be
regarded as logic variables, the phase shifts are obtained by using shift register
logic circuits driven by a clock pulse generator. Each shift register introduces a time
delay which depends on the number of bistables (or bits) in the register and the
clock pulse frequency. The required clock pulse frequency depends on the nominal
power system frequency.
5.2 Polarising arrangements
To simplify the description, the mho characteristic has been described in Section
5.1.1 as if it were self polarised. In fact, partial healthy phase cross polarising and
partial synchronous polarising components are used. The term synchronous
polarising refers to an advanced digital memory system which is described in
Section 5.2.2. These extra polarising components are used in order to satisfy the
following requirements:
1) To maintain a correct polarising (ie. directional reference) signal for the relay
comparators under conditions of close-up faults of all types even in the presence
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