SERVICE MANUAL R5888C
QUADRAMHO Chapter 2
Page 34 of 74
1) If signal A leads signal B, when A changes it gains the opposite state from B,
while when B changes it gains the same state as A.
2) If signal A lags signal B, when A changes it gains the same state as B, while
when B changes it gains the opposite state from A.
The comparator has a logic circuit which examines the input signals at each
change of state to see which of the two statements is true and thus determines
whether the sequence is progressing in a restrain or a tripping direction. The circuit
can identify the direction of the progression from a single change of logic state of
either input and from any starting point in the logic sequence.
Because the presence of noise can introduce false changes of state unconnected
with the true signals at the power system frequency, a single change of state
matching the trip sequence does not necessarily represent a fault condition within
the protected section of line. Greater security is obtained if the criterion for tripping
is to receive a number of successive changes of state, each of which matches the
tripping sequence. The comparator therefore has a counter for determining
whether one, two, three or four such changes have been observed.
Each acceptable change matching the tripping sequence adds to the total count
(up to a maximum of four) while every change matching the restrain sequence,
subtracts from the total count (down to a minimum of zero). The criterion for
operation is a count of three. The action of the counter for a typical fault within
Zone 1 is shown in Figure 31.
5.1.2 Action of the comparator counter
Figures 30 and 31 show pure power frequency signals, but it is obvious that the
presence of noise would change the situation. To illustrate the point, Figure 32
shows a restrain condition of the power frequency signals, with a burst of high
frequency noise superimposed on a comparator input. Because the noise happens
to coincide with a change of state of the other comparator input, a count up
situation occurs at high frequency. To prevent the comparator from tripping
wrongly, the rate of counting up is deliberately limited, preventing a count of more
than one from being registered.
The device for restricting the rate of counting up is a timing circuit. This is initiated
by any change of state which fits the tripping sequence and runs for a nominal
time period of 0.15 cycle. If another change of state in the operate sequence
occurs while the timer is running, the timer is restarted. While the timer is running,
the counter cannot be incremented further. Each change of state in the restrain
sequence decrements the counter and terminates any timing period running, so
there is no restriction on the rate of counting down.
The restriction on the rate of counting up effectively limits the operating bandwidth
of the comparator, eliminating maloperation on high frequency interference.
The same restriction also prevents the possibility of transient overreach occurring
when the V–
IZ comparator input has an exponential offset which distorts the mark/
space ratio of the square wave, as shown in Figure 33 Note that the exponential
component of the current does not cause a significant exponential offset in
IZ,
because the signal is differentiated with a short time constant by the current input
devices (transphasors) described later. The voltage supply can have an exponential
component which is reflected in V–
IZ but not in V
POL
because the latter is normally
dominated by healthy phase components.
The distance relay contains a total of eighteen full comparators, that is, three
ground fault and three phase fault comparators per zone. Each full comparator
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