Alstom SHPM 101 - Section 4. MODULE DESCRIPTIONS; 4.9.45 Loop timers

SERVICE MANUAL R5888C
QUADRAMHO Chapter 2
Page 23 of 74
registers are designated timer run out registers (TROR) and contain the timer run
out bits.
The timer start bit is set in the main loop when the timer is required to run.
Similarly this bit is set when the timer is to be reset. When the appropriate timer is
serviced by the timer interrupt, the timer start bit will be tested to see if the timer is
to be run. If a run condition is required then the timer will perform a counting
sequence in a register that has been designated a timer register.
The count within this register is incremented every time the timer is serviced by the
timer interrupt routine (every 1.974ms). When the timer has reached the required
count, the timer routine sets a bit in the timer run out register, this is the timer run
out bit. Every time the program executes the main loop the timer run out bit will be
tested to see if the timer has finished. If a reset condition is required, the timer run
out bit and the timer register are reset when the timer is next serviced by the
interrupt routine. Thus the timer is ready to be run when required. A list of all the
interrupt timers is given in Table 4.
Each of the 16 timers is allocated at least one timer register; long timers such as
the VTS 5.5s timer require more than one timer register.
The settable Zone 2 and Zone 3 delayed trip timers use multiples of a basic timer
length (eg. Z2 basic length is 10ms). The appropriate switches are used to provide
the multiplication factor. There is a 17th interrupt timer which is used to generate
the 2 week automatic self check delay.
4.9.45 Loop timers
Several of the shorter timers used within the scheme logic are loop timers.
These timers are run completely within the main loop. The operating principle of
these timers is described below.
When the timer is required to run, a register which is designated a timer register is
incremented once every time the main loop is executed. This is then tested to
determine if the timer has finished, if it has, then the timer register is reset. A list of
all the loop timers is given in Table 5.
TIMER FUNCTION TIMER LENGTH TIMER RESOLUTION
SIGNAL RECEIVE DROP OFF 100ms
td 0 – 90ms 6ms
tp 0 – 90ms 6ms
BLOCK AUTO 100ms –
RECLOSE DROP OFF
ANY POLE DEAD 240ms –
DROP OFF
VTS ACCELERATED 20ms –
INDICATION PICK UP
SYNCHRONOUS 140ms –
POLARISING (MEMORY)
ENABLE PICK UP
(POR) CIRCUIT BREAKER 60ms –
OPEN PICK UP
SOTF DEAD TIME 200ms or 110s –
SOTF ENABLE TIME 240ms –