Preliminary Technical Data UG-1828
Rev. PrC | Page 285 of 338
LDO mode 5 (LDO in bypass mode): An LDO is not required and is placed into bypass mode via software control. However, the power
domain is still required, and the customer applies a high efficiency power source at the Input pin. The purpose of this mode is to allow the
user to use higher efficiency power sources to supply the ADRV9001, as opposed to having the power overhead of associated with an
LDO.
In Table 111 Each of the 19 LDOs is listed and constraints provided to explain when each can be powered on, off or bypassed.
Table 111. LDO Constraints
Constraints Input Pin Output Pin
0
Do not power down or bypass. VANA1_1P3 VANA1_1P0
1
Do not power down or bypass. VANA2_1P3 VANA2_1P0
2
Power down only if all ADCs and DACs need to be powered down.
VCONV_1P3 VCONV_1P0
3
Power down if RX1 is not needed. VRX1LO_1P3 VRX1LO_1P0
Power down if TX1 is not needed.
5
Do not bypass. VANA2_1P3 VANA2_1P0
6
Power down if RX2 is not needed. VRX2LO_1P3 VRX2LO_1P0
7
Power down if TX2 is not needed. VTX2LO_1P3 VTX2LO_1P0
8
Power down if the CLK_PLL_LP is in use VCLKSYN_1P3
N/A
9
Power down if the CLK_PLL_LP is in use
VCLKVCO_1P0
10
Power down if the CLK_PLL is in use VCLKSYN_1P3
N/A
11
Power down if the CLK_PLL is in use
VCLKVCO_1P0
12
Power down if LO1 is being externally supplied VRFSYN1_1P3
N/A
13
Power down if LO1 is being externally supplied VRFVCO1_1P3
VRFVCO1_1P0
14
Power down if LO2 is being externally supplied VRFSYN2_1P3
N/A
15
Power down if LO2 is being externally supplied VRFVCO2_1P3
VRFVCO2_1P0
16
Power down if the AUX_PLL is not required.
N/A
17
Power down if the AUX_PLL is not required.
VAUXVCO_1P0
18
Do not power down or bypass. VDIG_1P0 VDIG_0P9
The three different configurations, as shown in Figure 266, can be set up in this function by setting the LDO modes as per Table 111 and
Table 112.
Table 112. Power saving configuration for each LDO
Configuration 0
1
1 1 1
2
5 5 1
3
5 5 1
4
5 5 1
5
1 1 1
6
5 5 1
7
5 5 1
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