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*TST?
Performs a self test of the instrument data memory. Returns 0 if it is successful or 1 if the test fails.
*CLS
Clears the Status Byte summary register and event registers. Does not clear the Enable registers.
*OPC
Sets the operation complete bit (bit 0) in the Standard Event register after a command is completed
successfully.
*OPC?
Returns an ASCII “1” after the command is executed.
*WAI
After the command is executed, this prevents the instrument from executing any further query or
commands until the no-operation-pending ag is TRUE.
*ESR?
Queries the Standard Event register. Returns the decimal value of the binary-weighted sum of bits.
*ESE <value>
Standard Event enable register controls which bits will be logically ORed together to generate the Event
Summary bit 5 (ESB) within the Status Byte.
*ESE?
Queries the Standard Event enable register. Returns the decimal value of the binary-weighted sum of
bits.
*STB?
Reads the Status Byte. Returns the decimal value of the binary-weighted sum of bits.
*SRE <value>
Service Request enable register controls which bits from the Status Byte should be used to generate a
service request when the bit value = 1.
*SRE?
Queries the Service Request enable register. Returns the decimal value of binary-weighted sum of bits.
*PSC {1|0}
Sets the power-on status clear bit. When set to 1 the Standard Event Enable register and Status Byte
enable registers will be cleared when power is turned ON. 0 setting indicates the Enable registers will be
loaded with Enable register masks from non-volatile memory at power ON.
*PSC?
Queries the power-on status clear setting. Returns 0 or 1.
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