Astrodesign VG-879 - Page 63

Chapter 4 Digital Output Settings (DIGITAL OUTPUT)
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■ Amount of data that can be transferred (pixel clock upper limit)
The amount of data that can be transferred (pixel clock upper limit) differs depending on the link rate, lane count, and output bit width.
Link Configuration
Maximum Pixel Clock
Link Rate
Lane Count
18 bpp
24 bpp
30 bpp
36 bpp
HBR2 (5.4 Gbps)
4 lanes
960 MHz
720 MHz
576 MHz
480 MHz
2 lanes
480 MHz
360 MHz
288 MHz
240 MHz
1 lane
240 MHz
180 MHz
144 MHz
120 MHz
HBR (2.7 Gbps)
4 lanes
480 MHz
360 MHz
288 MHz
240 MHz
2 lanes
240 MHz
180 MHz
144 MHz
120 MHz
1 lane
120 MHz
90 MHz
72 MHz
60 MHz
RBR (1.62 Gbps)
4 lane
288 MHz
216 MHz
172.8 MHz
144 MHz
2 lane
144 MHz
108 MHz
86.4 MHz
72 MHz
1 lane
72 MHz
54 MHz
43.2 MHz
36 MHz
* The values included in this table are the standard values (theoretical values). A pixel clock that exceeds the
specifications of the VG-876 and VG-879 units cannot be output.
For details, refer to “4.2.9 Relationship between Pattern Rendering Bit Length and Dot Clock”.