Atmel AT90S8515-8PI - Page 66

AT90S4414/8515
66
Figure 54. Port D Schematic Diagram (Pin PD1)
Figure 55. Port D Schematic Diagram (Pins PD2 and PD3)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
RP
RL
MOS
PULL-
UP
PD1
R
R
WP:
WD:
RL:
RP:
RD:
TXD:
TXEN:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
UART TRANSMIT DATA
UART TRANSMIT ENABLE
DDD1
PORTD1
TXEN
TXD