163
7679H–CAN–08/08
AT90CAN32/64/128
• Bit 7..2 – Reserved Bits
These bits are reserved for future use.
• Bit 1 – OCF2A: Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the
data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic
one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare match Interrupt
Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Inter-
rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
14.11 Timer/Counter2 Prescaler
Figure 14-13. Prescaler for Timer/Counter2
The clock source for Timer/Counter2 is named clk
T2S
. clk
T2S
is by default connected to the main
system I/O clock clk
IO
. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously
clocked from the TOSC oscillator or TOSC1 pin. This enables use of Timer/Counter2 as a Real
Time Counter (RTC).
A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an indepen-
dent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz
crystal. Setting AS2 and resetting EXCLK enables the TOSC oscillator.
10-BIT T/C PRESCALER
TIMER/COUNTER2 CLOCK SOURCE
clk
I/O
clk
T2S
AS2
CS20
CS21
CS22
clk
T2S
/8
clk
T2S
/64
clk
T2S
/128
clk
T2S
/1024
clk
T2S
/256
clk
T2S
/32
0
PSR2
Clear
clk
T2
0
1
TOSC2
EXCLK
0
1
AS2
EXCLK
32 kHz
Oscillator
Enable
TOSC1
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