369
7679H–CAN–08/08
AT90CAN32/64/128
26.5 Two-wire Serial Interface Characteristics
Table 26-3 describes the requirements for devices connected to the Two-wire Serial Bus. The
AT90CAN32/64/128 Two-wire Serial Interface meets or exceeds these requirements under the
noted conditions.
Timing symbols refer to Figure 26-3.
Notes: 1. In AT90CAN32/64/128, this parameter is characterized and not 100% tested.
Table 26-3. Two-wire Serial Bus Requirements
Symbol Parameter Condition Min Max Units
VIL
Input Low-voltage – 0.5 0.3 Vcc V
VIH
Input High-voltage 0.7 Vcc Vcc + 0.5 V
Vhys
(1)
Hysteresis of Schmitt Trigger Inputs 0.05 Vcc
(2)
–V
VOL
(1)
Output Low-voltage 3 mA sink current 0 0.4 V
tr
(1)
Rise Time for both SDA and SCL
20 + 0.1C
b
(3)(2)
300 ns
tof
(1)
Output Fall Time from V
IHmin
to V
ILmax
10 pF < C
b
< 400 pF
(3)
20 + 0.1C
b
(3)(2)
250 ns
tSP
(1)
Spikes Suppressed by Input Filter 0 50
(2)
ns
I
i
Input Current each I/O Pin 0.1 V
CC
< V
i
< 0.9 V
CC
– 10 10 µA
C
i
(1)
Capacitance for each I/O Pin – 10 pF
f
SCL
SCL Clock Frequency f
CK
(4)
> max(16f
SCL
, 250kHz)
(5)
0 400 kHz
Rp Value of Pull-up resistor
f
SCL
≤ 100 kHz
f
SCL
> 100 kHz
t
HD;STA
Hold Time (repeated) START Condition
f
SCL
≤ 100 kHz 4.0 – µs
f
SCL
> 100 kHz 0.6 – µs
t
LOW
Low Period of the SCL Clock
f
SCL
≤ 100 kHz
(6)
4.7 – µs
f
SCL
> 100 kHz
(7)
1.3 – µs
t
HIGH
High period of the SCL clock
f
SCL
≤ 100 kHz 4.0 – µs
f
SCL
> 100 kHz 0.6 – µs
t
SU;STA
Set-up time for a repeated START
condition
f
SCL
≤ 100 kHz 4.7 – µs
f
SCL
> 100 kHz 0.6 – µs
t
HD;DAT
Data hold time
f
SCL
≤ 100 kHz 0 3.45 µs
f
SCL
> 100 kHz 0 0.9 µs
t
SU;DAT
Data setup time
f
SCL
≤ 100 kHz 250 – ns
f
SCL
> 100 kHz 100 – ns
t
SU;STO
Setup time for STOP condition
f
SCL
≤ 100 kHz 4.0 – µs
f
SCL
> 100 kHz 0.6 – µs
t
BUF
Bus free time between a STOP and
START condition
f
SCL
≤ 100 kHz 4.7 – µs
V
CC
0,4V–
3mA
----------------------------
1000ns
C
b
-------------------
V
CC
0,4V–
3mA
----------------------------
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