Atmel AVR AT90CAN32

21
7679H–CAN–08/08
AT90CAN32/64/128
Figure 4-2. Data Memory Map
4.2.2 SRAM Data Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU
cycles as described in Figure 4-3.
Figure 4-3. On-chip Data SRAM Access Cycles
32 Registers
64 I/O Registers
Internal SRAM
(ISRAM size)
0x0000 - 0x001F
0x0020 - 0x005F
XMem start
ISRAM end
0xFFFF
0x0060 - 0x00FF
Data Memory
External SRAM
(XMem size)
160 Ext I/O Reg.
ISRAM start
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction