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7679H–CAN–08/08
AT90CAN32/64/128
17. USART (USART0 and USART1)
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device. The main features are:
17.1 Features
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High Resolution Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode
17.2 Overview
Many registers and bit references in this section are written in general form.
• A lower case “n” replaces the USART number, in this case 0 or 1. However, when using the
register or bit defines in a program, the precise form must be used, i.e., UDR0 for accessing
USART0 I/O data value and so on.
17.3 Dual USART
The AT90CAN32/64/128 has two USART’s, USART0 and USART1. The functionality for both
USART’s is described below. USART0 and USART1 have different I/O registers as shown in
“Register Summary” on page 405.
A simplified block diagram of the USARTn Transmitter is shown in Figure 17-1. CPU accessible
I/O Registers and I/O pins are shown in bold.
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