425
7679H–CAN–08/08
AT90CAN32/64/128
19.12 Examples of CAN Baud Rate Setting .............................................................266
20 Analog Comparator ............................................................................. 269
20.1 Overview .........................................................................................................269
20.2 Analog Comparator Register Description .......................................................269
20.3 Analog Comparator Multiplexed Input ............................................................271
21 Analog to Digital Converter - ADC ..................................................... 273
21.1 Features ..........................................................................................................273
21.2 Operation ........................................................................................................274
21.3 Starting a Conversion .....................................................................................275
21.4 Prescaling and Conversion Timing .................................................................276
21.5 Changing Channel or Reference Selection ....................................................279
21.6 ADC Noise Canceler .......................................................................................280
21.7 ADC Conversion Result ..................................................................................284
21.8 ADC Register Description ...............................................................................287
22 JTAG Interface and On-chip Debug System ..................................... 293
22.1 Features ..........................................................................................................293
22.2 Overview .........................................................................................................293
22.3 Test Access Port – TAP ..................................................................................293
22.4 TAP Controller ................................................................................................296
22.5 Using the Boundary-scan Chain .....................................................................297
22.6 Using the On-chip Debug System ..................................................................297
22.7 On-chip Debug Specific JTAG Instructions ....................................................298
22.8 On-chip Debug Related Register in I/O Memory ............................................299
22.9 Using the JTAG Programming Capabilities ....................................................299
22.10 Bibliography ....................................................................................................299
23 Boundary-scan IEEE 1149.1 (JTAG) ................................................... 300
23.1 Features ..........................................................................................................300
23.2 System Overview ............................................................................................300
23.3 Data Registers ................................................................................................300
23.4 Boundary-scan Specific JTAG Instructions ....................................................302
23.5 Boundary-scan Related Register in I/O Memory ............................................304
23.6 Boundary-scan Chain .....................................................................................304
23.7 AT90CAN32/64/128 Boundary-scan Order ....................................................314
23.8 Boundary-scan Description Language Files ...................................................320
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