Chapter: BIOS Settings Chipset
page 90 Beckhoff New Automation Technology CB3064-xxxx
6.4.2.1.2 PCI Express Root Port
Aptio Setup Utility - Copyright (C) 2017 American Megatrends, Inc.
Chipset
┌─────────────────────────────────────────────────────────────────┬────────────────────────────────┐
│ PCI Express Root Port 1 [Enabled] ▲│Control the PCI Express Root │
│ Topology [Unknown] █│Port. │
│ ASPM [Disabled] █│ │
│ L1 Substates [Disabled] █│ │
│ Gen3 Eq Phase3 Method [Software Search] █│ │
│ UPTP 5 █│ │
│ DPTP 7 █│ │
│ ACS [Enabled] █│ │
│ URR [Disabled] █│ │
│ FER [Disabled] █│ │
│ NFER [Disabled] █│ │
│ CER [Disabled] █│ │
│ CTO [Disabled] █│────────────────────────────────│
│ SEFE [Disabled] █│→←: Select Screen │
│ SENFE [Disabled] █│↑↓: Select Item │
│ SECE [Disabled] █│Enter: Select │
│ PME SCI [Enabled] █│+/-: Change Opt. │
│ Hot Plug [Disabled] █│F1: General Help │
│ Advanced Error Reporting [Enabled] █│F2: Previous Values │
│ PCIe Speed [Auto] █│F3: Optimized Defaults │
│ Transmitter Half Swing [Disabled] █│F4: Save & Exit │
│ Detect Timeout 0 █│ESC: Exit │
│ Extra Bus Reserved 0 █│ │
│ Reserved Memory 10 ░│ │
│ Reserved I/O 4 ░│ │
│ ▼│ │
└─────────────────────────────────────────────────────────────────┴────────────────────────────────┘
Version 2.18.1263. Copyright (C) 2017 American Megatrends, Inc.
PCI Express Root Port x
Options: Disabled / Enabled
Topology
Options: Unknown / x1 / x4 / Sata Express / M2
ASPM Support
Options: Disabled / L0s / L1 / L0sL1 / Auto
L1 Substates
Options: Disabled / L1.1 / L1.2 / L1.1 & L1.2
Gen3 Eq Phase3 Method
Options: Hardware / Static Coeff. / Software Search
UPTP
Options: 0..10
DPTP
Options: 0..10
ACS
Options: Enabled / Disabled
URR
Options: Enabled / Disabled
FER
Options: Enabled / Disabled
NFER
Options: Enabled / Disabled
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