Bosch BMP581 - Table 18: SPI Timings

Bosch Sensortec"| BST-BMP581-DS004-02 32 | 74
Modifications reserved | Data subject to change
without notice Document number: BST-BMP581-DS004-02
5.2.1 Interface timing
The timing diagram for SPI is given in Figure 7 and is valid for all SPI configurations. The corresponding values are
given in
Figure 7: SPI timing diagram (SPI4, Mode 0
Table 18: SPI timings
Parameter
Comment
Symbol
Unit
Target value
min
typ
max
CSB lag time
T_hold_csb
ns
40
SDX setup
time
T_setup_sdx
ns
19
SDX hold time
T_hold_sdx
ns
7
SCL to SDO
turnaround
time
90%/10% Master rise/fall time
= [2, 10]ns @ Cbus = 40pF,
drive_strength = 7
T_delay_scl2sdo_1p2
ns
52.5
90%/10% Master rise/fall time
= [2, 10]ns @ Cbus = 80pF,
drive_strength = 7
T_delay_scl2sdo_1p8
ns
27.8
90%/10% Master rise/fall time
= [2, 10]ns @ Cbus = 80pF,
drive_strength = 6
T_delay_scl2sdo_3p3
ns
20.2
SDO rise/fall
time (90%/
10%)
@ VDDIO = 1.2V
ns
tbd
@ VDDIO = 1.8V/3.3V
ns
10
SCX
frequency
@ VDDIO = 1.8 V/3.3 V
F_sck,nv
MHz
1
12
SCX Pulse
High Time
5% duty cycle variation
T_high_scx
ns
37.5
SCX Pulse
Low Time
T_low_scx
ns
37.5
Idle time after
write access
T_wr_idle, spi
ns
80
Idle time after
read access
T_rd_idle,spi
ns
80