Bosch BMP581 - Table 19: I3 C Timing Limitations for VDDIO < 1.62 V

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without notice Document number: BST-BMP581-DS004-02
5.2.2 I2C timing specifications
BMP581 follows the I²C specification for standard mode, fast mode and fast mode plus. For timing specifications, please
consult the „I2C-bus specification and user manual“, UM10204, Rev.6, NXP Semiconductors. This is valid for the entire
VDDIO voltage range.
5.2.3 I3C timing specifications
BMP581 follows the I3C specification for SDR mode. For timing specifications, please consult the „Specification for I3C
Version 1.1“ and the corresponding errata document „Errata 01 for MIPI I3C Specification“, both from the Mipi Alliance.
For VDDIO < 1.62V, there are deviations from the specification, which are summarized in Table 18.
Table 19: I3C timing limitations for VDDIO < 1.62 V
Parameter
Symbol
Condition
Min
Typ
Max
Units
SCL clock frequency
fSCL
VDDIO <
1.62V
0.1
2.5
MHz
Fall time of SDA signal
tFDA
35
ns
SDA Signal Data Setup in
Push-Pull Mode
t
SU_PP
5
Ns
Clock in to Data Out for Slave
t
SCO
215
Fall Time of SDA Signal
t
fDA_OD
35
ns