Bosch BMP581 - Table 23: I3 C Provisional Identifier; Table 24: I3 C Device Characteristics Register (DCR); Table 25: I3 C Bus Characteristics Registers (BCR)

Bosch Sensortec"| BST-BMP581-DS004-02 42 | 74
Modifications reserved | Data subject to change
without notice Document number: BST-BMP581-DS004-02
5.7 I3C Protocol
BMP581 supports the I³C protocol 1.0. Following I³C features are supported:
 I²C compatibility including:

Support of I2C-like SDR messages to the BMP581

bus traffic of I2C messages to legacy I2C slaves

I3C single data rate (SDR) mode with up to 12.5 MHz data rate

In-Band Interrupt (IBI)

Timing control asynchronous 0 mode (restricted to maximum 11 MHz I3C frequency and a minimum of 200 kHz)

Timing control synchronous mode
The I3C bus uses the pin SCL for serial clock and SDX as SDA for serial data input and output for the signal lines.
5.7.1 I3C Identifiers
The I3C protocol uses several identifiers and codes to handle communication between several masters and slaves. For
communication with this device, there are defined the I3C provisional ID, the Device Characteristics Register (DCR), the
Bus Characteristics Register (BCR) and the Mandatory Byte (MDB) for IBIs. The I3C provisional ID has the value defined
in Table 20.
Table 23: I3C provisional identifier
The value of the Device Characteristics Register (DCR) is fixed to 0x62 to indicate a pressure sensor, as shown in Table
21. See also https://www.mipi.org/MIPI_I3C_device_characteristics_register
.
Table 24: I3C device characteristics register (DCR)
DCR<7>
DCR<6>
DCR<5>
DCR<4>
DCR<3>
DCR<2>
DCR<1>
DCR<0>
Device ID
0
1
1
0
0
0
1
0
The value of the Bus Characteristics Register (BCR) is fixed to 0x06, as shown in Table 22.
Table 25: I3C bus characteristics registers (BCR)
BCR <7:6>
BCR <5>
BCR <4>
BCR <3>
BCR <2>
BCR <1>
BCR <0>
I3C Slave
Reserved
Not a bridge
Device will
always respond
to I3C Bus
commands
Mandatory
payload after IBI
IBI capable
Max data Speed:
no limitation
2’b00
1’b0
1’b0
1’b0
1’b1
1’b1
1’b0
5.7.2 I3C In-band Interrupts
The device supports the in-band interrupt (IBI) feature of I3C, as described in the I3C specification. In case there is an
IBI event, the device will emit its address into the arbitrated address header following a START (but not following a
repeated START).
If no START is forthcoming within the Bus Available Condition, then the chip will actively pull down the SDA line to issue
a START. The IBI feature can be enabled by the Common Command Code (CCC)’ ENEC with the ENINT bit set to
0b1.The IBI feature can be disabled by the Common Command Code (CCC)’ DISEC with the DISINT bit set to 0b1.