Bosch BMP581 - Table 22: SPI Interface Pin Usage

Bosch Sensortec"| BST-BMP581-DS004-02 36 | 74
Modifications reserved | Data subject to change
without notice Document number: BST-BMP581-DS004-02
5.4 Read burst address increment
For read bursts in all protocols, the BMP581 performs an automatic address increment with each read byte. That
means, if the user reads for example 10 bytes starting address 0x01, the BMP581 will return the data for register
0x01..0x0A. An exception to this rule is the FIFO_DATA register. If a read starts at FIFO_DATA, the address will not be
incremented, but the read will continue on the register to support FIFO read-out. The same applies if the FIFO_DATA
register is addressed during a read burst that started with an address below the FIFO_DATA register. For more
inforation on FIFO read-out, see Chapter 3.6.3 "FIFO data readout".
5.5 SPI Protocol
The SPI interface is compatible with SPI mode '00' (CPOL = CPHA = '0') and mode '11' (CPOL = CPHA = '1'). The
automatic selection between mode '00' and '11' is determined by the value of SCK after the CSB falling edge.
The SPI interface has two modes: 4-wire and 3-wire. The protocol is the same for both. The 3-wire mode is selected
by setting DRIVE_CONFIG.spi3_en = 1. The pad SDI is used as a data input/output pad in 3-wire mode.
Table 19 shows the usage of pins for the SPI protocol. MOSI refers to Master-Out, Slave-In data direction. MISO refers
to the Slave-In, Master-Out data direction.
Table 22: SPI interface pin usage
Name
Description
Function in 4-wire
mode
Function in 3-wire
mode
CSB
chip select, active low
chip select, active low
chip select, active low
SCK
serial clock
serial clock
serial clock
SDX
serial data in/output
MOSI data
MOSI and MISO data
SDO
serial data output
MISO data
--
Refer to Chapter 5 "Pin out and connection diagrams" for connection instructions.
Data on SDX is latched by the device at SCK rising edge and SDO is changed at SCK falling edge. Communication
starts when CSB goes to low and stops when CSB goes to high; during these transitions on CSB, SCK must be stable.
The SPI protocol is shown in the following subsections.
5.5.1 SPI3 Wire Mode
SDX must be left floating in SPI3 mode. The reason is that the device starts in SPI4 mode after power-up, and drives
SDX until the switch to SPI3 is commanded.
SDI must always be tied to either low or high voltage and not left floating, even when the CSB is high, and no
communication with the device takes place. A floating SDI may create excessive power consumption (and on the
longterm potentially also damage to the device).
5.5.2 SPI Write Operation
SPI write operation supports single-byte as well as multi-byte (burst) writing. Figure 7 shows the SPI single-byte write
protocol. The host sends the write command, write address, write data, and then terminates the transaction.