PRELIMINARY
Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 3
NPO: Filename: Number of pages: Page:
00109/04:V1729.MUTx/03 V1729_REV3.DOC 38 34
used to launch the readout of the MATACQ chips towards the RAM. The default value is
of 10μs whereas the minimum one is of 2,5μs.
POST LATENCY PRETRIG
: this register fixes with steps of 2.5μs the time given to the
MATACQ chips to get filled up again consequently to the restarting of the writing in the
mode using a validation signal. The default value as well as the minimum one are of
2,5μs.
INTERRUPT
: this register memorizes the arrival of the interruption which signals the end
of the acquisition phase. The INTERRUPT signal is forwarded towards the acquisition
buses, but it can also be read here. It is also here that it must be released and reset at
zero by a simple write access. It is anyhow reset by the START_ACQ command.
FP_FREQUENCY
: this 2-bit register permits fixing of the Fp period. It is initialized at 1.
Bits Function
0-1
Val = 1 => Fsample = 2GHz.
Val = 2 => Fsample = 1GHz.
FPGA VERSION :
this 8-bit read-only register permits reading of the version number of
the FPGA. The 3 MSbits give the type of board and the 5 LSbits the version number of
the firmware stored in the PROM. The code corresponding to the V1729 board is 3,
which gives a root number of h60 for FPGA VERSION.
EN_VME_IRQ :
this 1-bit register permits authorization (1) or not (0) of the output of the
interruption at the end of the acquisition towards the VME bus on VME_IRQ3.
NB OF BYTES TO READ IN BLOCK MODE
: for the readings in block mode by GPIB
solely, this 16-bit register permits fixing the number of bytes contained in the block. In
order to simplify the accesses by reading to the RAM, one will send as in the reading
order 4 bytes of data : the 1
st
with hFF, the 2
nd
and the 3
rd
with respectively the LSBs
then the MSBs of the number of bytes to read, and finally the 4
th
with the sub-address
h0C for the RAM. The MSBs then the LSBs will then be sent successively. Do not forget
to double the number of data to read in the RAM when passing from the number of words
to the number of bytes.
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