D01a_1009_Alex
SSC_DPLL_REF_CLKN
SSC_DPLL_REF_CLKP
SSC CLOCK TERMINATION STUFF
ONLY WHEN SSC CLOCK NOT USED
XD P_ TD O _R
XD P _D BR _R
PU/PD for JTAG signals
XD P_ TR S T#
XD P_ TM S
XD P_ TC L K
XD P_ P RE Q #
XD P_ TD I _ R
H_PROCHOT#
CAD Note: Capacitor need to be placed
close to buffer output pin
FC_AK31
PMSYS_PWRGD_BUF
C439
68P_50V_NPO_04
R11310K_1%_04
R694 *10K_04
R3791K_04
R397 *51_04
VDD3 13,19,20,21,23,24,25,26,27,29,34,36,37,40,41,42,45,46
C440
0.047u_10V_X7R_04
R438
3.32K_1%_04
R432
4.99K_1%_04
R389 51_04
Q41
MTN7002ZHS3
G
DS
Q54
*MTN7002Z HS3
G
DS
R59
*750_1%_04
R400 51_04
R423
*200_04
R425 75_1%_04
S
D
G
Q9A
MTDN7002ZHS6R
2
61
R38162_04
U31
*MC74VHC1G08DFT1G
1
2
5
4
3
R426
*39_04
C390
47P_50V_NPO_04
R427
1.82K_1%_04
R435 *0_04
Q26
MTN7002ZHS3
G
DS
S
D
G
Q9B
MTDN7002ZHS6R
5
34
R693 *0_06
C108 *0.1u_16V_Y5V_04
R402
*100K_04
R394 51_04
R395 51_04
R433 100_1%_04
R421 0_04
R385
100K_04
R436
1K_04
R696 *10K_04
C700
*22u_6.3V_X5R_08
R386 *1. 5K_1%_04
C441
*0.1u_16V_Y5V_04
R441 1K_04
H_PROCHOT#_R
R434 100_1%_04
R404 *100_04
R51 75_04
R390
100K_04
R60 43.2_1%_04
R95
10K_04
R405 51_04
C701
*22u_6.3V_X5R_08
VDDQ
R422
*100K_04
3.3V
3.3VS
1.05VS
3.3V
VDD Q
VCC IO_OUT
1.05VS
3.3VS
1.05VS
VCC IO_OUT
1.05VS 6,25, 26,30,42,44,62
DDR 3_DRAMRST# 9, 10,11,12
VDDQ 4,6, 9,10,11,12,30,39
3.3V 2,14,15,19, 29,30,32, 36,37,39, 41,42, 62
DRAMRST_CNTRL 4,20
PM_DRAM_PWRGD21
3.3VS 5,9,10,11,12,13, 14,16,17, 18,19,20, 21,22, 24,25,26, 27,28,29,30, 32,33,34, 35,36,37, 41,44,46,61, 62
PLT_RST#13,22, 46
SUSB13,39, 41,42
H_PROCHOT#_EC34
VCCI O_OUT 5,6, 44
S3 circuit:- DRAM PWR GOOD logic
CPUDRAMRST#
H_PROCHOT#
SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0
BUF_CPU_RST#
H_CPUPWRGD_R
BSS138 ( VGS 1.5V )
Haswell Processor 2/7 ( MISC,JTAG,CLK )
XD P_ TD O _R
Processor Pullups/Pull downs
TRACE WIDTH 10MIL, LENGTH <500MILS
DDR3 Compensation Signals
S3 circuit:- DRAM_RST# to memory
should be high during S3
Buffered reset to CPU
H_PROCHOT#_R
PCH_PLTRST_CPU
H_PROCHOT# H_PROCHOT#_R
D01a_1009_Alex
H_CPUPWRGD_RH_CPUPWRGD
FC_AK31
DPLL_REF_CLKN
R114 *10mil_s hort
DPLL_REF_CLKP
R409 0_04
PWR
DDR3L
MIS C
THE RM A L CLO C K
JTAG
Haswel l rPGA EDS
2 OF 9
U32B
FC_AK31
AK31
PM_SY NC
AT28
PWR GOOD
AL34
BPM_N_7
AP28
BPM_N_6
AP29
BPM_N_5
AN28
BPM_N_4
AP30
BPM_N_3
AP31
BPM_N_2
AN29
BPM_N_1
AN31
BPM_N_0
AR30
DBR
AP33
TD O
AL33
TDI
AM31
TRST
AM33
TMS
AN33
TCK
AM34
PREQ
AT29
PRD Y
AR29
SM_DR AMRST
AN3
SM_RCOMP_2
AP2
SM_RCOMP_1
AR3
SM_RCOMP_0
AP3
BCLKP
E26
BCLKN
D26
SSC_DPLL_REF_CLKP
E27
SSC_DPLL_REF_CLKN
F27
DPLL_REF_CLKP
H28
DPLL_REF_CLKN
G28
PROC HOT
AM30
PECI
AR27
CATERR
AN32
SKTOCC
AP32
PLTRSTI N
AT26
SM_DR AMPWR OK
AC10
THE RMTR I P
AM35
H_PECI
R413 0_04
R691 *1K_04
R415 0_04
R139 *10mil_s hort
R692 0_04
R380 56_1%_04
R412 0_04
R414 0_04
R128 *10mil_s hort
R61 *10mil_short
1.05VS
H_PECI24,34
CLK_EXP_N27
CLK_EXP_P27
H_PM_SYNC21
H_THRMTRIP#24
H_PROCHOT#44
PCH_PLTRST_CPU24
H_CPUPWRGD24
H_ THRMTR IP# _R
SM_RC OMP_0
CLK_ EXP_N
CLK_ EXP_P
H _THRM TRIP #
XD P_ TM S
XD P_ TR S T#
XD P_ TC L K
SM_RC OMP_2
SM_RC OMP_1
XD P_ P RE Q #
XD P_ TD I _ R
XD P_ TD O _R
CPUDRAMRST#
H_CATERR#
XD P_ B PM2
XD P_ B PM3
XD P_ B PM4
XD P_ B PM5
XD P_ B PM6
XD P_ B PM7
SKTOCC#
XDP_PRDY#
XD P_ D BR _ R
XD P_ B PM0
XD P_ B PM1
SSC_DPLL_REF_CLKN
SSC_DPLL_REF_CLKP
PMSYS_PWR GD_BUF VDDPW RGOOD_R
CPU_RST#
H_PM_SYNC H_PM_SYNC_R
R700 *0_04
CRB 0905
CRB 0905
CLK_DPNS_N27
CLK_DP_P27
CLK_DP_N27
BUF_CPU_RST#
D01A_1018_Alex
CLK_DPNS_P27
D02_1116_Alex
R418 *100_04
H_THRMTRIP#
D01A_1018_Alex
CRB 0906
CRB 0905
Gary D03 valueÅܧó0103
C123 1u_6. 3V_X5R_04
D02_1105_Alex
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