CFG[6:5]=11 for x16
Stanley
[Note]Processor strap CFG[4] should be pulled low to enable Embedded DisplayPort
PM_PCH_PWROK
CFG16
RSVD_E20
TESTLO_W 34
CFG8
CFG7
CFG6
RSVD_AT2
R81 *1K_04
R707 49.9_1%_04
Haswel l rPGA EDS
9 OF 9
U32I
VSS
AR26
VSS
AP27
RSVD
AD10
RSVD_TP
AT2
RSVD_TP
A34
RSVD_TP
A35
RSVD
P10
RSVD
U10
NC
B1
RSVD_TP
E20
RSVD_TP
E21
RSVD
A2
RSVD
E18
RSVD_TP
AR1
RSVD
K6
RSVD
AM2
RSVD
F5
RSVD
AM26
RSVD
AM27
CFG_19
AP23
CFG_17
AP21
CFG_18
AR23
CFG_16
AR21
CFG_RCOMP
AT31
RSVD_TP
D23
RSVD_TP
D24
RSVD_TP
B23
RSVD_TP
C23
CFG_15
AP25
CFG_14
AN26
CFG_13
AN25
CFG_9
AT23
CFG_8
AR24
CFG_7
AN23
CFG_6
AT25
RSVD_TP
B35
RSVD_TP
C35
RSVD_TP
AT1
CFG_12
AP26
CFG_11
AP24
CFG_10
AN20
RSVD
AR33
FC_G6
G6
RSVD_TP
AL25
RSVD_TP
W30
RSVD_TP
W31
TESTLO_W34
W34
CFG_0
AT20
CFG_1
AR20
CFG_4
AT22
CFG_5
AN22
CFG_3
AP22
CFG_2
AP20
VSS
AL31
VSS
AL32
RSVD_TP
W28
RSVD_TP
W29
VCC
F25
VSS
W33
TESTLO_G26
G26
RSVD
AL30
RSVD
AL29
R709
*2K_1%_04
R82 *1K_04
CFG0
R83 *1K_04
R710
*1K_1%_04
R84 1K_04
R85 *1K_04
R708 49.9_1%_04
R706 49.9_1%_04
VCORE6,7,44
PM_PCH_PW ROK 21
VCORE
TESTLO_G2 6
TESTLO_G26
RSVD_W30
CFG9
RSVD_A34
CFG17
RSVD_E21
CFG2
CFG18
CFG11
CFG10
CFG6
CFG5
CFG4
Haswell Processor 7/7 ( RESERVED )
RSVD_B23
RSVD_C23
CFG7
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
CFG2
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG[6:5]
CFG4
PCIE PORT BIFURCATION STRAPS
CFG7
DISPLAY PORT PRESENCE STRAP
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
DEFENSIVE PULL DOWN SITE
RSVD_AL25
CFG1
RSVD_D24
RSVD_W29
Reserve this circuit for future compatibility
RSVD_AR1
CFG_RCOMP
CFG13
CFG12
RSVD_A35
RSVD_D23
RSVD_W28
FC_G6
CFG14
FC_G6
RSVD_W31
RSVD_B35
CFG2
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG19
CFG5
CFG4
RSVD_AT1
CFG_RCOMP
CFG15
CFG STRAPS FOR PROCESSOR
TESTLO_W34
RSVD_C35
CFG3
R103 *1K_04
CFG3