Clevo P170SM - Processor 3;7 Schematic

Schematic Diagrams
Processor 3/7 B - 5
B.Schematic Diagrams
Processor 3/7
SB_D IMM_VREFD Q
M_B _B 4
M_B _B 6
M_B _B 5
M_B _B 13
M_B _B 12
M_B _B 0
M_B _B 1
M_B _B 2
M_B _B 3
M_B _B 7
M_B _B 8
M_B _B 9
M_B _B 10
M_B _B 11
M_B _B 14
M_B _B 15
SM_VREF_RSM_VRE F
RSVD_AC7
SA_D IMM_VREFD Q
R431
*1K_04
SB_D IMM_VREFD Q
R442
1K_1%_04
R429
1K_1%_04
R416 0_04
R699
1K_1%_04
R446
1K_1%_04
R698
1K_1%_04
Q36
*AO3402L
G
DS
Q37
*AO3402L
G
DS
R443 0_04
Q56
*AO3402L
G
DS
R430 0_04
Haswe ll rP GA EDS
3 OF 9
U32C
VSS
V10
SA_BS_0
V5
SA_BS_1
U5
SA_DQ_48
B5
SA_CKP1
V3
SA_CS_N_1
L9
SA_CS_N_2
M9
SA_CS_N_3
M10
SA_ODT_0
M8
SA_ODT_1
L7
SA_ODT_2
L8
SA_ODT_3
L10
SA_BS_2
AD 1
SA_RAS
U6
SA_WE
U7
SA_CAS
U8
SA_MA_0
V8
SA_MA_1
AC 6
SA_MA_10
V6
SA_MA_11
AC 1
SA_MA_12
AD 4
SA_MA_13
V7
SA_MA_14
AD 3
SA_MA_15
AD 2
SA_MA_2
V9
SA_MA_3
U9
SA_MA_4
AC 5
SA_MA_5
AC 4
SA_MA_6
AD 6
SA_MA_7
AC 3
SA_MA_8
AD 5
SA_MA_9
AC 2
SA_DQS_N _0
AP15
SA_DQS_N _1
AP8
SA_DQS_N _2
AJ 8
SA_DQS_N _3
AF 3
SA_DQS_N _4
J3
SA_DQS_N _5
E2
SA_DQS_N _6
C5
SA_DQS_N _7
C11
SA_DQS_P_0
AP14
SA_DQS_P_1
AP9
SA_DQS_P_2
AK8
SA_DQS_P_3
AG3
SA_DQS_P_4
H3
SA_DQS_P_5
E3
SA_DQS_P_6
C6
SA_DQS_P_7
C12
SA_DQ_0
AR15
SA_DQ_1
AT14
SA_DQ_2
AM14
SA_DQ_3
AN14
SA_DQ_4
AT15
SA_DQ_5
AR14
SA_DQ_6
AN15
SA_DQ_7
AM15
SA_DQ_8
AM9
SA_DQ_9
AN9
SA_DQ_10
AM8
SA_DQ_11
AN8
SA_DQ_12
AR9
SA_DQ_13
AT9
SA_DQ_14
AR8
SA_DQ_15
AT8
SA_DQ_16
AJ9
SA_DQ_17
AK9
SA_DQ_18
AJ6
SA_DQ_19
AK6
SA_DQ_20
AJ10
SA_DQ_21
AK10
SA_DQ_22
AJ7
SA_DQ_23
AK7
SA_DQ_24
AF4
SA_DQ_25
AF5
SA_DQ_26
AF1
SA_DQ_27
AF2
SA_DQ_28
AG4
SA_DQ_29
AG5
SA_DQ_30
AG1
SA_DQ_31
AG2
SA_DQ_32
J1
SA_DQ_33
J2
SA_DQ_34
J5
SA_DQ_35
H5
SA_DQ_36
H2
SA_DQ_37
H1
SA_DQ_38
J4
SA_DQ_39
H4
SA_DQ_43
D3
SA_DQ_60
E11
SA_DQ_61
D11
SA_DQ_62
B12
SA_DQ_63
A12
SM_VREF
AM3
SA_DIMM_VREFDQ
F16
SB_DIMM_VREFDQ
F13
SA_DQ_40
F2
SA_DQ_41
F1
SA_DQ_42
D2
SA_DQ_44
D1
SA_DQ_46
C3
SA_DQ_47
B3
SA_DQ_49
E6
SA_DQ_59
A11
SA_DQ_58
B11
SA_DQ_57
D12
SA_DQ_56
E12
SA_DQ_55
A6
SA_DQ_54
B6
SA_DQ_53
E5
SA_DQ_52
D5
SA_DQ_51
D6
SA_DQ_50
A5
SA_DQ_45
F3
SA_CKE_0
AD 9
SA_CKP0
V4
SA_CKN1
U3
SA_CKE_1
AC 9
SA_CKN2
U2
SA_CKP2
V2
SA_CKE_2
AD 8
SA_CKN3
U1
SA_CKE_3
AC 8
SA_CKP3
V1
SA_CS_N_0
M7
SA_CKN0
U4
RSVD
AC 7
R482
1K_1%_04
Has well rPGA ED S
4 OF 9
U32D
VSS
R10
SB_DQ _32
L2
SB_DQ _34
L4
SB_DQ _36
L1
SB_DQ _37
M1
SB_CKE_2
AG9
SB_CKE_3
AF9
SB_CS_N_0
P4
SB_CS_N_1
R2
SB_CS_N_2
P3
SB_CS_N_3
P1
SB_OD T_0
R4
SB_OD T_1
R3
SB_OD T_2
R1
SB_OD T_3
P2
SB_BS_0
R7
SB_BS_1
P8
SB_BS_2
AA9
SB_R AS
R6
SB_WE
P6
SB_C AS
P7
SB_MA_0
R8
SB_MA_1
Y5
SB_MA_2
Y10
SB_MA_3
AA5
SB_MA_4
Y7
SB_MA_5
AA6
SB_MA_6
Y6
SB_MA_7
AA7
SB_MA_8
Y8
SB_MA_9
AA10
SB_MA_10
R9
SB_MA_11
Y9
SB_MA_12
AF7
SB_MA_13
P9
SB_MA_14
AA8
SB_MA_15
AG7
SB_DQS_N _0
AP18
SB_DQS_N _1
AP11
SB_DQS_N _2
AP5
SB_DQS_N _3
AJ3
SB_DQS_N _4
L3
SB_DQS_N _5
H9
SB_DQS_N _6
C8
SB_DQS_N _7
C14
SB_DQS_P_0
AP17
SB_DQS_P_1
AP12
SB_DQS_P_2
AP6
SB_DQS_P_3
AK3
SB_DQS_P_4
M3
SB_DQS_P_5
H8
SB_DQS_P_6
C9
SB_DQS_P_7
C15
SB_DQ _0
AR18
SB_DQ _1
AT18
SB_DQ _2
AM17
SB_DQ _3
AM18
SB_DQ _4
AR17
SB_DQ _5
AT17
SB_DQ _6
AN17
SB_DQ _7
AN18
SB_DQ _8
AT12
SB_DQ _9
AR12
SB_DQ _10
AN12
SB_DQ _11
AM11
SB_DQ _12
AT11
SB_DQ _13
AR11
SB_DQ _14
AM12
SB_DQ _15
AN11
SB_DQ _16
AR5
SB_DQ _17
AR6
SB_DQ _18
AM5
SB_DQ _19
AM6
SB_DQ _20
AT5
SB_DQ _21
AT6
SB_DQ _22
AN5
SB_DQ _23
AN6
SB_DQ _24
AJ4
SB_DQ _25
AK4
SB_DQ _26
AJ1
SB_DQ _27
AJ2
SB_DQ _38
L5
SB_DQ _39
M5
SB_DQ _40
G7
SB_DQ _41
J8
SB_DQ _42
G8
SB_DQ _45
J9
SB_DQ _46
G10
SB_DQ _47
J10
SB_DQ _48
A8
SB_DQ _49
B8
SB_DQ _50
A9
SB_DQ _51
B9
SB_DQ _52
D8
SB_DQ _53
E8
SB_DQ _54
D9
SB_DQ _55
E9
SB_DQ _56
E15
SB_DQ _57
D15
SB_DQ _58
A15
SB_DQ _59
B15
SB_DQ _60
E14
SB_DQ _61
D14
SB_DQ _62
A14
SB_DQ _63
B14
SB_DQ _35
M4
SB_DQ _33
M2
SB_DQ _31
AK1
SB_DQ _30
AK2
SB_DQ _29
AN1
SB_DQ _28
AM1
SB_DQ _44
J7
SB_DQ _43
G9
RSVD
AG8
SB_CKE_1
AG10
SB_CKE_0
AF10
SB_CKN0
Y4
SB_CKN1
Y3
SB_CKN2
Y2
SB_CKN3
Y1
SB_CKP0
AA4
SB_CKP1
AA3
SB_CKP2
AA2
SB_CKP3
AA1
R495
*1K_04
VDDQ
M_A_CKE1 9
VDD Q
VDD Q
M_A_DQS#[7: 0] 9,10
M_A_ CS# 1 9
M_A_ CS# 0 9
M_A_CLK_DDR#0 9
M_A_CLK_DDR0 9
M_A_CKE0 9
M_A_DQS[7: 0] 9, 10
M_A_ ODT0 9
M_A_ ODT1 9
M_B _CKE 0 1 2
M_B _CL K_DD R#1 12
M_B _CL K_DD R1 1 2
M_B _CKE 1 1 2
M_B _ODT1 12
M_B _CL K_DD R#0 12
M_B _CL K_DD R0 1 2
M_B_CS#1 12
M_B_CS#0 12
M_B _ODT0 12
M_A_CS#2 10
M_A_CKE3 10
M_A_CKE2 10
M_A_ ODT2 1 0
M_A_ ODT3 1 0
M_A_CS#3 10
M_B _CKE 2 1 1
M_B _CL K_DD R#3 11
M_B _CL K_DD R3 1 1
M_B _CKE 3 1 1
M_B_CS#2 11
M_B _CL K_DD R#2 11
M_B _CL K_DD R2 1 1
M_B _ODT2 11
M_B _ODT3 11
M_B_CS#3 11
M_A_CLK_DDR#3 10
M_A_CLK_DDR3 10
M_A_A[15:0] 9,10
M_A_CLK_DDR1 9
M_A_CLK_DDR#2 10
M_A_CLK_DDR2 10
M_A_ BS2 9, 10
M_A_ BS1 9, 10
M_A_ BS0 9, 10
M_A_CLK_DDR#1 9
M_A_CAS# 9,10
M_A_ WE# 9 ,10
M_A_RAS# 9,10
M_B _BS1 11 ,12
M_B _BS0 11 ,12
M_B_B[15:0] 11,12
M_B_RAS# 11,12
M_B _BS2 11 ,12
M_B_CAS# 11,12
MVREF_DQ_DIMMA 9,10
DRAMRST_CNTRL 3,20
M_B_WE# 11,12
M_A_DQ[63:0]9,10
M_B_DQS#[7:0] 11,12
M_B_DQS[7: 0] 11,12
MVREF_DQ_DIMMB 11, 12
VDDQ3,6,9 ,10,11,12,30,39
SM_VRE F_R 9,11
M_ B_D Q [6 3 :0 ]11,12
SM_VREF
RSVD_AG8
M_A_A5
M_A_A7
M_A_A8
M_A_A9
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A6
M_A_A1 2
M_A_A1 1
M_A_A1 3
M_A_A1 4
M_A_A1 5
All VREF traces should be at least 20 mils wide
and 20 mils spacing to other singals/planes
DRAMRST_CNTRL
M_A_A1 0
M_A _DQ2 9
M_A _DQ4
M_A _DQ3
M_A _DQ2
M_A _DQ1
M_A _DQ3 5
M_A _DQ3 4
M_A _DQ3 3
M_A _DQ3 2
M_A _DQ3 1
M_A _DQ3 0
M_A _DQ4 1
M_A _DQ4 0
M_A _DQ3 9
M_A _DQ3 7
M_A _DQ3 6
M_A _DQ4 6
M_A _DQ4 5
M_A _DQ4 4
M_A _DQ4 3
M_A _DQ4 2
M_A _DQ5 1
M_A _DQ2 8
M_A _DQ5 0
M_A _DQ4 9
M_A _DQ3 8
M_A _DQ4 7
M_A _DQ4 8
M_A _DQ5 5
M_A _DQ5 4
M_A _DQ5 3
M_A _DQ5 2
M_A _DQ5 8
M_A _DQ5 7
M_A _DQ5 6
M_A _DQ6
M_A _DQ5
M_A _DQ7
M_A _DQ5 9
M_A _DQ6 3
M_A _DQ6 2
M_A _DQ6 1
M_A _DQ6 0
M_A _DQ1 2
M_A _DQ1 1
M_A _DQ9
M_A _DQ8
M_A _DQ1 8
M_A _DQ1 7
M_A _DQ1 6
M_A _DQ1 5
M_A _DQ1 4
M_A _DQ1 3
M_A _DQ2 2
M_A _DQ2 1
M_A _DQ1 0
M_A _DQ1 9
M_A _DQ2 7
M_A _DQ2 6
M_A _DQ2 5
M_A _DQ2 4
M_A _DQ2 3
M_A _DQ0
M_B _D Q 50
M_B _D Q 49
M_B _D Q 48
M_B _D Q 47
M_A _DQ2 0
M_B _D Q 55
M_B _D Q 54
M_B _D Q 53
M_B _D Q 52
M_B _D Q 51
M_B _D Q 61
M_B _D Q 60
M_B _D Q 59
M_B _D Q 58
M_B _D Q 57
M_B _D Q 56
M_B _D Q 1
M_B _D Q 12
M_B _D Q 11
M_B _D Q 63
M_B _D Q 62
M_B _D Q 6
M_B _D Q 5
M_B _D Q 4
M_B _D Q 3
M_B _D Q 2
M_B _D Q 10
M_B _D Q 9
M_B _D Q 8
M_B _D Q 7
M_B _D Q 17
M_B _D Q 16
M_B _D Q 15
M_B _D Q 14
M_B _D Q 13
M_B _D Q 0
M_B _D Q 22
M_B _D Q 21
M_B _D Q 20
M_B _D Q 19
M_B _D Q 18
M_B _D Q 27
M_B _D Q 26
M_B _D Q 25
M_B _D Q 24
M_B _D Q 23
M_B _D Q 33
M_B _D Q 32
M_B _D Q 31
M_B _D Q 30
M_B _D Q 29
M_B _D Q 28
M_B _D Q 38
M_B _D Q 37
M_B _D Q 36
M_B _D Q 35
M_B _D Q 34
M_B _D Q 43
M_B _D Q 42
M_B _D Q 41
M_B _D Q 40
M_B _D Q 39
M_A_C KE1
M_A_C LK_DDR1
M_A_C LK_DDR# 1
M_B _D Q 46
M_B _D Q 45
M_B _D Q 44
M_A_D QS#5
M_A_D QS#6
M_A_D QS#7
M_A_C S#1
M_A_C S#0
M_A_D QS#0
M_A_D QS#2
M_A_D QS#1
M_A_D QS#3
M_A_D QS#4
M_A_OD T0
M_A_C LK_DDR# 0
M_A_C LK_DDR0
M_A_C KE0
M_A_D QS4
M_A_D QS5
M_A_D QS6
M_A_D QS7
M_A_OD T1
M_A_BS 0
M_A_D QS0
M_A_D QS2
M_A_D QS1
M_A_D QS3
M_A_W E#
M_A_R AS#
M_A_C AS#
M_A_BS 2
M_A_BS 1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#6
M_B_DQS#5
M_B_DQS5
M_B_DQS#7
M_B_DQS#0
M_B_DQS#1
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS6
M_B_CKE1
M_B _C L K_ DD R # 1
M_B _C L K_ DD R 1
M_B_DQS7
M_B_DQS0
M_B _O D T1
M_B _O D T0
M_B _C L K_ DD R # 0
M_B _C L K_ DD R 0
M_B_CKE0
M_A_C LK_DDR2
M_A_C LK_DDR# 2
M_A_C KE2
M_B _C S #1
M_B _C S #0
M_A_OD T2
M_A_C S#3
M_A_C S#2
M_A_C LK_DDR3
M_A_C LK_DDR# 3
M_A_C KE3
M_B_CKE2
M_B_CKE3
M_B _C L K_ DD R # 3
M_B _C L K_ DD R 3
M_A_OD T3
M_B _O D T2
M_B _C S #3
M_B _C S #2
M_B _C L K_ DD R # 2
M_B _C L K_ DD R 2
M_B _O D T3
MVR EF_ DQ_ DI MMB
¾aDIMMºÝÂ\©ñ
SA_DIMM_VREFDQ MVREF_DQ_DIMMA
Haswell Processor 3/7 ( DDR3L )
M_B_CAS#
M_B _B S2
M_B _B S0
M_B _B S1
M_B _W E #
M_B_RAS#
Sheet 4 of 60
Processor 3/7