Technical Reference Manual
Page 27 of 38
PT-3000
2.1.3 Chipset Features Setup Menu
ROM PCI/ISA BIOS <2A5IIAKA>
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Auto Configuration: Enabled
L2 (WB) Tag Bit Length: 8bits
SRAM Back-to-Back: Enabled
NA# Enable: Enabled
Starting Point of Paging: 1T
Refresh Cycle Time (us): 187.2
RAS Pulse Width Refresh: 6T
RAS Precharge Time: 4T
RAS to CAS Delay: 4T
RAMW# Assertion Timing: 3T
SDRAM WR Retire Rate: X-2-2-2
SDRAM Wait State Control: 1WS
Enhanced Memory Write: Disabled
Read Prefetch Memory RD: Enabled
CPU to PCI Port Write : 3T
CPU to PCI Burst Mem. WR: Disabled
ISA Bus Clock Frequency: PCICLK/4
System BIOS Cacheable :Enabled
Video BIOS Cacheable :Enabled
Esc :Quit :Select Item
F1 :Help PU/PD/+/- :Modify
F5 :Old Value (Shift)F2 :Color
F6 :Load BIOS Defaults
F7 :Load Setup Defaults
The parameters in this screen are to configure the system based on the specific
features of the installed chipset. This chipset manages bus speeds and access to
system memory resources, such as DRAM and the external cache. It also coordinates
communications between the conventional ISA bus and the PCI bus. Do not reset
these values unless you understand the consequences of your changes.
Auto Configuration, selects predetermined optimal values of chipset parameters.
When disabled, chipset parameters revert to setup information stored in CMOS. Many
fields in this screen are not available when auto configuration is enabled.
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