Cypress CY7C68013 - Page 3

CY7C68013
Document #: 38-08012 Rev. *A Page 3 of 48
LIST OF FIGURES
Figure 1-1. Block Diagram ....................................................................................................................5
Figure 3-1. Internal Code Memory, EA = 0.........................................................................................11
Figure 3-2. External Code Memory, EA = 1........................................................................................12
Figure 3-3. Endpoint Configuration ...................................................................................................14
Figure 4-1. Signals...............................................................................................................................18
Figure 4-2. CY7C68013 128-pin TQFP Pin Assignment....................................................................19
Figure 4-3. CY7C68013 100-pin TQFP Pin Assignment....................................................................20
Figure 4-4. CY7C68013 56-pin SSOP Pin Assignment .....................................................................21
Figure 9-1. Program Memory Read Timing Diagram ........................................................................36
Figure 9-2. Data Memory Read Timing Diagram ............................................................................... 37
Figure 9-3. Data Memory Write Timing Diagram...............................................................................38
Figure 9-4. GPIF Synchronous Signals Timing Diagram
[12]
.............................................................39
Figure 9-5. Slave FIFO Synchronous Read Timing Diagram
[12]
.......................................................40
Figure 9-6. Slave FIFO Asynchronous Read Timing Diagram
[12]
..................................................... 41
Figure 9-7. Slave FIFO Synchronous Write Timing Diagram
[12]
.......................................................41
Figure 9-8. Slave FIFO Asynchronous Write Timing Diagram
[12]
..................................................... 42
Figure 9-9. Slave FIFO Synchronous Packet End Strobe Timing Diagram
[12]
................................42
Figure 9-10. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
[12]
............................43
Figure 9-11. Slave FIFO Output Enable Timing Diagram
[12]
.............................................................43
Figure 9-12. Slave FIFO Address to Flags/Data Timing Diagram
[12]
................................................ 43
Figure 9-13. Slave FIFO Synchronous Address Timing Diagram ...................................................44
Figure 9-14. Slave FIFO Asynchronous Address Timing Diagram
[12]
............................................. 44
Figure 11-1. 56-lead Shrunk Small Outline Package O56 ................................................................ 45
Figure 11-2. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 ....................................46
Figure 11-3. 128-Lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128..................................47