Cypress CY7C68013 - Page 4

CY7C68013
Document #: 38-08012 Rev. *A Page 4 of 48
LIST OF TABLES
Table 3-1. Default ID Values for FX2 ...................................................................................................8
Table 3-2. INT2 USB Interrupts ............................................................................................................9
Table 3-3. Individual FIFO/GPIF Interrupt Sources ..........................................................................10
Table 3-4. Default Full-Speed Alternate Settings
[1, 2]
........................................................................14
Table 3-5. Default High-Speed Alternate Settings
[1, 2]
......................................................................15
Table 3-6. Strap Boot EEPROM Address Lines to These Values ...................................................17
Table 4-1. FX2 Pin Descriptions
[5]
......................................................................................................22
Table 5-1. FX2 Register Summary .....................................................................................................29
Table 8-1. DC Characteristics ............................................................................................................35
Table 8-2. USB Transceiver ...............................................................................................................35
Table 9-1. Program Memory Read Parameters ................................................................................36
Table 9-2. Data Memory Read Parameters .......................................................................................37
Table 9-3. Data Memory Write Parameters .......................................................................................38
Table 9-4. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
[13, 14]
..............39
Table 9-5. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
[14]
.................39
Table 9-6. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK
[14]
............40
Table 9-7. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK
[14]
..........40
Table 9-8. Slave FIFO Asynchronous Read Parameters
[15]
.............................................................41
Table 9-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
[14]
..........41
Table 9-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK
[14]
.......42
Table 9-11. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
[15]
......42
Table 9-12. Slave FIFO Synchronous Packet End Strobe Parameters
with Internally Sourced IFCLK
[14]
......................................................................................................42
Table 9-13. Slave FIFO Synchronous Packet End Strobe Parameters
with Externally Sourced IFCLK
[14]
.....................................................................................................43
Table 9-14. Slave FIFO Asynchronous Packet End Strobe Parameters
[15]
....................................43
Table 9-15. Slave FIFO Output Enable Parameters .........................................................................43
Table 9-16. Slave FIFO Address to Flags/Data Parameters ............................................................44
Table 9-17. Slave FIFO Synchronous Address Parameters
[14]
.......................................................44
Table 9-18. Slave FIFO Asynchronous Address Parameters
[15]
......................................................44
Table 10-1. Ordering Information ......................................................................................................44