93
automatically clears the register and sets all bits to inactive state or 0. When querying an Event
register the information is returned as a decimal number representing the binary-weighted sum of
all bits within the register.
The Enable registers bits represent the selection of bits that will be logically OR’d together to form
the summary bit in the Status Byte. The *CLS command will not clear the Enable registers and if
you wish to clear the register you must set it to a value of 0. Like the Event register, the enable
register is represented as a decimal number that equals the binary-weighted sum of all bits.
The Enable register will clear to value a of 0 at power up unless the *PSC 0 command had been
executed before power-off. The *PSC command tells the device whether or not it should clear the
Enable registers at power-on. Using this command will allow SQRs to function immediately after
power-on.
Request Service (RQS) or
Master Summary Status (MSS)
8.4.9 GPIB Service Request
The service request capability is not available with the USB/RS-232 interface. The SRQ line will be
activated only after one or more of the service request functions have been enabled using the
Status Byte Enable register command *SRE.
The Status Byte bit assignments are as described in the previous section for status reporting.
When the instrument has requested service, the enabled bit or bits and the RQS bit 6 will be active
or 1. Bits 4, 5, and 7 are not used and will be set to false, or 0 for all Status Byte reads.
After the serial poll (SPOLL) is executed the RQS bit will be cleared to 0, and the remaining bits will
remain unchanged. The Status Byte will not change value until the event register is read and
cleared for the corresponding Status Byte bit.
For example after the All Pass SRQ has been enabled, when the test(s) have finished with pass
indications the instrument will set the hardware SRQ line and output the Status Byte of 41 hex.
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