91
00H=OK
01H=TEST EEPROM ERROR
Clear Standard Event Status Register
Clear Service Request Register
Operation Complete Command
When all selected pending
operations complete, ESR BIT0=1
When all selected pending
operations complete, Output
Queue=1
Power-on Status Clear Command
1 = Power-on clear enable registers
0 = Power-on load previous enable
registers
Power-on Status Clear Query
Standard Event Status Register Query
Standard Event Status Enable
Command
Standard Event Status Enable Query
Service Request Enable Command
Service Request Enable Query
*IDN?
Read the instrument identification string. Company = EEC
*RST
Reset the instrument to original power on configuration. Does not clear Enable register for
Standard Summary Status or Standard Event Registers. Does not clear the output queue. Does not
clear the power-on-status-clear flag.
*TST?
Performs a self-test of the instrument data memory. Returns 0 if it is successful or 1 if the test
fails.
*CLS
Clears the Status Byte Summary register and Event registers. Does not clear the Enable registers.
*OPC
Sets the operation complete bit (bit 0) in the Standard Event register after a command is
completed successfully.