Tau User’s Manual Appendix B—Serial Communication Technical Details
TAU-0035-00-10, version 100 April 2009 B-13
B.9 Digital Data Channels
The camera provides two digital ports.
• Port 1 consists of the signals SD_CLK+, SD_FSYNC+, and SD_DATA+.
• Port 2 consists of the signal LVDS_VID0+
, LVDS_VID1+, and LVDS_VID2+.
Note
All signals in the digital data interface employ low-voltage differential signaling (LVDS).
The clock rate of DATA_CLK+
is 73.636 MHz.
The timing of the digital data interface is shown in Figure B-1 and Figure B-3.
The format of the digital output shall be is in Figure B-2.
14-bit and 8-bit timing and format are identical except only 8 bits (LSBs) are available in 8-bit
mode.
Port 2 is currently undefined—do not connect to these signals
Figure B-1: Digital Data Timing
F = frame sync; logic high on the word starting the frame, logic low otherwise
L = line sync; logic high during valid pixel data, logic low otherwise
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