processor. See Figure 6-22. The loading starts when PROGN
is set low. The FPGA responds with a negative pulse on
INITN and setting DONE low. After loading 1442016 bits,
which takes approximat e ly 2.2 s, the FPGA sets DONE high if
the loading was successful. If an error is detected, INITN is
set low. One clock pulse after DONE is set high all I/Os on the
FPGA are defined. If the loading of the FPGA is not success-
ful, the program just goes on with the rest of the startu p
procedure.
The fan is set to 8.4 V. See Figure 6-23. Measure on J19 or
J28. The input amplifiers are initialized and a "click" from the
relays is heard. The I
2
C bus is used for controlling the relays.
Note: The I
2
C bus is of the utmost importance for the start of
the instrument. The FPGA, the LCD and the relays in
the input amplifiers all need a faultless I
2
C bus to work
properly.
Note: If the Flash PROM is exchanged, it must be replaced
by a preprogrammed Flash PROM. Voltage and
timebase calibration must be performed anew. The
utility program must be used for transferring the cali
-
bration results to new factory calibrations. The serial
number and the oscillator option must also be pro
-
grammed by the utility program.
The fan is kept at +8.4 V for the first 8.3 minutes. After that
the fan is temperature controlled. The processor reads the
temperature via the I
2
C bus every 10th second. IC U39 mea
-
sures the temperature.
The keys on the display board are read over the I
2
C bus. If a
key is pressed, the I
2
C bus circuit U3 notices that and sends an
interrupt to the processor. Check at J13:9; low is interrupt.
The processor then scans the keys via the I
2
C bus to find the
depressed key. See Figure 6 -30. During the scanning there
may appear some extra interrupts. This is not an error condi-
tion.
6-16 Troubleshooting
Figure 6-18 Important locations on PCB 1 during startup.
J19
R492
J28
U39
X33
Figure 6-19 Important locations on PCB 2 during startup.
X3
X2
X5
X1
R33
U3
R34
X4
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