GE F650 - Page 242

GEK-106310AB F650 Digital Bay Controller 5-95
5 SETTINGS 5.5 CONTROL ELEMENTS
5
Table 5–79: SYNCHRONISM CONDITIONS
Table 5–79: shows the different synchrocheck and closing logic situations, that can be produced depending on the line and
busbar voltage levels.
Live Line – Live Bus (Synchronism check): Only in case number (2), with live line and live bus, the element will start
evaluating the line and busbar voltage comparison with respect to the setting ΔV
set
established by setting (Max Volt Difference). In this case, if the voltage difference is
lower than ΔV
set
, the synchronism check element (25) will verify the angle difference
Δϕ adjusted by setting (Max Angle Difference).
Dead Line – Dead Bus (DL - DB): Case number (3) will not allow the synchronism function, but it will allow DL-DB
operation logic, if this logic is enabled by setting (DL-DB Function).
Dead Line – Live Bus (DL - LB): Case number (6) will not allow the synchronism function, but it will allow DL-LB
Operation logic, if this logic is enabled by setting (DL-LB Function)
Live Line – Dead Bus (LL - DB): Case number (7) will not allow the synchronism function, but it will allow LL-DB
operation logic, if this logic is enabled by setting (LL-DB Function)
Case numbers (1), (4) and (5) are not considered neither for synchronism check purposes, nor for closing logic.
SYNCHRONISM SITUATION SYNCHRONISM
CHECK
CLOSING LOGIC LINE VOLTAGE
LEVELS
BUSBAR VOLTAGE
LEVELS
(1) V
L
< (V
1
& V
2
)< V
H
Not permitted Not permitted V1 > dead line level
V1 < live line level
V2 > dead bus level
V2 < live bus level
(2) (V
1
& V
2
) > V
H
Permitted Live Line – Live Bus V1 > live line level V2 > live bus level
(3) (V
1
& V
2
) < V
L
Not permitted Dead Line – Dead Bus V1 < dead line level V2 < dead bus level
(4) (V
1
< V
L
) & (V
L
< V
2
< V
H
) Not permitted Not permitted V1 < dead line level V2 > dead bus level
V2 < live bus level
(5) (V
2
< V
L
) & (V
L
< V
1
< V
H
) Not permitted Not permitted V1 > dead line level
V1 < live line level
V2 < dead bus level
(6) (V
1
< V
L
) & (V
2
> V
H
) Not permitted Dead Line – Live Bus V1 < dead line level V2 > live bus level
(7) (V
2
< V
L
) & (V
1
> V
H
) Not permitted Live Line – Dead Bus V1 > live line level V2 < dead bus level