4 Trip On Close Schemes 259
4.1 Switch On To Fault (SOTF) 260
4.1.1 Switch Onto Fault Mode 260
4.1.2 SOTF Tripping 261
4.1.3 SOTF Tripping with CNV 261
4.2 Trip On Reclose (TOR) 261
4.2.1 Trip On Reclose Mode 262
4.2.2 TOR Tripping Logic for Appropriate Zones 262
4.2.3 TOR Tripping Logic with CNV 262
4.3 Polarisation during Circuit Engergisation 262
5 Zone1 Extension Scheme 264
6 Loss of Load Scheme 265
Chapter 10 Power Swing Functions 267
1 Chapter Overview 269
2 Introduction to Power Swing Blocking 270
3 Power Swing Blocking 272
3.1 Power Swing Detection 272
3.1.1 Settings-Free Power Swing Detection 272
3.1.2 Slow Power Swing Detection 275
3.2 Detection of a Fault During a Power Swing 276
3.3 Power Swing Blocking Configuration 276
3.4 Power Swing Load Blinding Boundary 277
3.5 Power Swing Blocking Logic 278
3.6 Power Swing Blocking Setting Guidelines 279
3.6.1 Setting the Resistive Limits 280
3.6.2 Setting the Reactive Limits 280
3.6.3 PSB Timer Setting Guidelines 281
4 Out of Step Protection 283
4.1 Out of Step Detection 283
4.2 Out of Step Protection Operataing Principle 284
4.3 Out of Step Logic Diagram 285
4.4 OST Application Notes 285
4.4.1 Setting the OST Mode 285
Chapter 11 Autoreclose 293
1 Chapter Overview 295
2 Introduction to Autoreclose 296
3 Autoreclose Implementation 297
3.1 Autoreclose Logic Inputs from External Sources 298
3.1.1 Circuit Breaker Healthy Input 298
3.1.2 Inhibit Autoreclose Input 298
3.1.3 Block Autoreclose Input 298
3.1.4 Reset Lockout Input 299
3.1.5 Pole Discrepancy Input 299
3.1.6 External Trip Indication 299
3.2 Autoreclose Logic Inputs 299
3.2.1 Trip Initiation Signals 299
3.2.2 Circuit Breaker Status Inputs 299
3.2.3 System Check Signals 299
3.3 Autoreclose Logic Outputs 299
3.4 Autoreclose Operating Sequence 300
3.4.1 AR Timing Sequence - Transient Fault 300
3.4.2 AR Timing Sequence - Evolving/Permanent Fault 300
3.4.3 AR Timing Sequence - Evolving/Permanent Fault Single-phase 301
4 Autoreclose System Map 302
P543i/P545i Contents
P54x1i-TM-EN-1 vii