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10.7
FIF
TH HARMONIC BLOCKING LOGIC
V0
2619
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* Inter
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Figure 45: Fifth Harmonic Blocking logic
Chapter 6 - Current Differ
ential Protection
P543i/P545i
122
P54x1i-TM-EN-1
157
159
Table of Contents
Table of Contents
3
Table of Figures
27
Chapter 1 Introduction
37
Section 3
39
Default Chapter
39
Chapter Overview
39
Foreword
40
Target Audience
40
Typographical Conventions
40
Compliance
41
Nomenclature
41
Product Scope
42
Product Versions
42
Figure 1: P40L Version M85 - Version Evolution
43
Ordering Options
43
Current Differential Protection Functions
44
Distance Protection Functions
44
Features and Functions
44
Protection Functions
44
Control Functions
45
Communication Functions
46
Measurement Functions
46
Logic Diagrams
47
Figure 2: Key to Logic Diagrams
48
Figure 3: Functional Overview
49
Functional Overview
49
Chapter 2 Safety Information
51
Chapter Overview
53
Health and Safety
54
Symbols
55
Installation, Commissioning and Servicing
56
Lifting Hazards
56
Electrical Hazards
56
UL/CSA/CUL Requirements
57
Fusing Requirements
57
Equipment Connections
58
Protection Class 1 Equipment Requirements
58
Pre-Energisation Checklist
59
Peripheral Circuitry
59
Upgrading/Servicing
60
Decommissioning and Disposal
61
Regulatory Compliance
62
EMC Compliance: 2014/30/EU
62
LVD Compliance: 2014/35/EU
62
R&TTE Compliance: 2014/53/EU
62
UL/CUL Compliance
62
ATEX Compliance: 2014/34/EU
62
Chapter 3 Hardware Design
65
Section 4
67
Default Chapter
67
Chapter Overview
67
Coprocessor Hardware Architecture
68
Figure 4: Hardware Architecture
68
Hardware Architecture
68
Figure 5: Coprocessor Hardware Architecture
69
Figure 6: Exploded View of IED
70
Housing Variants
70
Mechanical Implementation
70
List of Boards
71
Figure 7: Front Panel (60TE)
73
Front Panel
73
Front Panel Compartments
73
Front Serial Port (SK1)
74
Keypad
74
Fixed Function Leds
75
Front Parallel Port (SK2)
75
Function Keys
75
Programable Leds
76
Figure 8: Rear View of Populated Case
77
Rear Panel
77
Figure 9: Terminal Block Types
78
Boards and Modules
79
Figure 10: Rear Connection to Terminal Block
79
Pcbs
79
Subassemblies
79
Figure 11: Main Processor Board
80
Main Processor Board
80
Figure 12: Power Supply Board
81
Power Supply Board
81
Figure 13: Power Supply Assembly
82
Figure 14: Power Supply Terminals
83
Watchdog
83
Figure 15: Watchdog Contact Terminals
84
Rear Serial Port
84
Figure 16: Rear Serial Port Terminals
85
Figure 17: Input Module - 1 Transformer Board
85
Input Module - 1 Transformer Board
85
Figure 18: Input Module Schematic
86
Input Module Circuit Description
86
Figure 19: Transformer Board
87
Transformer Board
87
Figure 20: Input Board
88
Input Board
88
Figure 21: Standard Output Relay Board - 8 Contacts
89
Standard Output Relay Board
89
Figure 22: IRIG-B Board
90
IRIG-B Board
90
Fibre Optic Board
91
Figure 23: Fibre Optic Board
91
Ethernet Board
92
Figure 24: Rear Communication Board
92
Figure 25: Ethernet Board
92
Rear Communication Board
92
Figure 26: Redundant Ethernet Board
94
Redundant Ethernet Board
94
Coprocessor Board
96
Coprocessor Board with 1PPS Input
96
Current Differential Inputs
96
Figure 27: Fully Populated Coprocessor Board
96
Chapter 4 Software Design
99
Section 5
101
Default Chapter
101
Chapter Overview
101
Figure 28: Software Architecture
102
Sofware Design Overview
102
Real Time Operating System
103
Self-Diagnostic Software
103
Startup Self-Testing
103
System Boot
103
System Level Software
103
System Services Software
103
Continuous Self-Testing
104
Platform Software Initialisation and Monitoring
104
System Level Software Initialisation
104
Interfaces
106
Platform Software
106
Record Logging
106
Settings Database
106
Acquisition of Samples
107
Direct Use of Sample Values
107
Frequency Tracking
107
Protection and Control Functions
107
System Level Software Initialisation
107
Distance Protection
108
Figure 29: Frequency Response of FIR Filters
108
Fourier Signal Processing
108
Figure 30: Frequency Response (Indicative Only)
109
Programmable Scheme Logic
109
Disturbance Recorder
110
Event Recording
110
Fault Locator
110
Chapter 5 Configuration
111
Section 6
113
Default Chapter
113
Chapter Overview
113
Settings Application Software
114
Using the HMI Panel
115
Figure 31: Navigating the HMI
116
Default Display
117
Figure 32: Default Display Navigation
118
Password Entry
119
Menu Structure
120
Changing the Settings
121
Direct Access (the Hotkey Menu)
122
Circuit Breaker Control
123
Figure 33: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
125
Line Parameters
125
Residual Compensation
126
Date and Time Configuration
128
Without a Timing Source Signal
129
Daylight Saving Time Compensation
130
Settings Group Selection
131
Chapter 6 Current Differential Protection
133
Section 7
135
Default Chapter
135
Chapter Overview
135
Current Differential Protection Principle
136
Figure 34: Ping-Pong Measurement for Alignment of Current Signals
138
Synchronisation of Current Signals
138
GPS Synchronisation
139
Figure 35: Asymmetric Propogation Delay Times
140
Figure 36: Dual Slope Current Differential Bias Characteristic
141
Phase Current Differential Protection
141
Phase Current Differential Tripping Criteria
142
Figure 37: Phase Current Differential Protection Logic
143
Neutral Current Differential Protection
144
Three-Terminal Schemes
145
Three-Terminal Scheme Reconfiguration on Energisation
146
Transient Bias
147
Figure 38: Capacitive Charging Current
148
Capacitive Charging Current Compensation
148
Figure 39: CT Compensation
149
CT Compensation
149
Feeders with In-Zone Transformers
150
Zero Sequence Filtering
151
Figure 40: the Need for Zero-Sequence Current Filtering
152
Magnetising Inrush Restraint
152
Figure 41: Magnetising Inrush Phenomenon
153
Second Harmonic Restraint
153
Figure 42: Typical Overflux Current Waveform
155
Overfluxing Restraint
155
Figure 43: Phase Current Differential Protection Logic for Feeders with In-Zone Transformers
156
Figure 44: Second Harmonic Blocking Logic
157
Figure 45: Fifth Harmonic Blocking Logic
158
Figure 46: Permissive Intertripping Example
159
Current Differential Intertripping
159
Figure 47: Stub Bus Protection
160
Stub Bus Differential Protection
160
Application Notes
161
Sensitivity under Heavy Loads
162
Permissive Intertripping
163
Feeders with Small Tapped Loads
164
Figure 48: Typical Two-Terminal Plain Feeder Circuit
165
Setting a Three-Terminal Phase Current Differential Element
165
Figure 49: Typical Three-Terminal Plain Feeder Circuit
166
Chapter 7 Distance Protection
169
Chapter Overview
171
Figure 50: System Impedance Ratio
172
Introduction
172
Impedance Calculation
173
Distance Measuring Zones Operating Principles
174
Figure 51: Directional Mho Element Construction
175
Mho Characteristics
175
Directional Self-Polarized Mho Characteristic for Earth Faults
176
Figure 52: Offset Mho Characteristic
176
Figure 53: Directional Mho Element Construction - Impedance Domain
177
Figure 54: Offset Mho Characteristics - Impedance Domain
178
Offset Mho Characteristic for Earth Faults
178
Figure 55: Offset Mho Characteristics - Voltage Domain
179
Figure 56: Simplified Forward Fault
180
Memory Polarization of Mho Characteristics
180
Figure 57: Mho Expansion - Forward Fault
181
Figure 58: Simplified Reverse Fault
182
Cross Polarization of Mho Characteristics
183
Figure 59: Mho Contraction - Reverse Fault
183
Implementation of Mho Polarization
184
Figure 60: Simplified Quadrilateral Characteristics
185
Quadrilateral Characteristic
185
Directional Quadrilaterals
186
Figure 61: General Quadrilateral Characteristic Limits
186
Figure 62: Directional Quadrilateral Characteristic
187
Figure 63: Quadrilateral Characteristic Featuring 2 Directional Forward Zones and 1 Offset Zone
188
Figure 64: Five-Sided Polygon Formed by Quadrilateral Characteristic with Directional-Line
189
Earth Fault Quadrilateral Characteristics
190
Figure 65: Impedance Reach Line in Z1 Plane
192
Figure 66: Impedance Reach Line in ZLP Plane
193
Figure 67: General Characteristic in ZLP Plane
194
Figure 68: Phase Relations between I2 and Iph for Leading and Lagging Polarizing Currents
195
Figure 69: General Characteristic in Z1 Plane
196
Figure 70: Simplified Characteristic in Z1 Plane
197
Quadrilateral Characteristic for Phase Faults
198
Figure 71: Impedance Reach Line Construction
199
Phase Fault Impedance Reach Line
199
Figure 72: Reverse Impedance Reach Line Construction
200
Figure 73: Resistive Reach of Phase Elements
200
Phase Fault Resistive Reach Line
200
Figure 74: Resistive Reach Line Construction
201
Figure 75: Reverse Resistive Reach Line Construction
202
Figure 76: Phase Fault Quadrilateral Characteristic Summary
202
Phase Fault Reverse Resistive Reach Line
202
Phase and Earth Fault Distance Protection Implementation
204
Distance Protection Phase Selection
205
Biased Neutral Current Detector
206
Figure 77: Phase to Phase Current Changes for C Phase-To-Ground (CN) Fault
206
Distance Element Zone Settings
207
Figure 78: Biased Neutral Current Detector Characteristic
207
Advanced Distance Zone Settings
208
Capacitor VT Applications
209
Figure 79: Load Blinder Characteristics
210
Load Blinding
210
Cross Country Fault Protection
211
Delta Directional Element
212
Figure 80: Sequence Networks Connection for an Internal A-N Fault
213
Delta Directional Decision
213
Figure 81: - DV Forward and Reverse Tripping Regions
214
Figure 82: Current Level (Amps) at Which Transient Faults Are Self-Extinguishing
215
Distance Isolated and Compensated Systems
215
Figure 83: Earth Fault in Petersen Coil Earthed System
216
Figure 84: Distribution of Currents During a Phase C Fault
216
Figure 85: Phasors for a Phase C Earth Fault in a Petersen Coil Earthed System
217
Figure 86: Zero Sequence Network Showing Residual Currents
217
Figure 87: Phase C Earth Fault in Petersen Coil Earthed System: Practical Case with Resistance
218
Earth Fault Distance Protection for Isolated and Compensated Systems
218
Single-Phase to Earth Faults on Isolated or Compensated Systems
219
Implementation of Distance Protection for Isolated and Compensated Networks
220
Figure 88: Voltage Distribution in an Isolated System for a Phase-A-To-Earth Fault
221
Figure 89: Biased Neutral Current Detector
221
Fault Detection Logic
222
Figure 90: First Earth Fault Detection
222
Figure 91: Second Earth Fault Detection Logic
223
Phase Preferential Logic
223
Figure 92: Priority Setting Enable Logic
225
Figure 93: Zone Starting Logic
226
Figure 94: Zone Timer Logic
227
Figure 95: Zone Trip Logic
228
Figure 96: Settings Required to Apply a Quadrilateral Zone
229
Application Notes
229
Earth Fault Characteristic
230
Figure 97: Settings Required to Apply a Mho Zone
230
Quadrilateral Resistive Reaches
231
Dynamic Tilting
232
Figure 98: Over-Tilting Effect
232
Fixed Tilting
233
Directional Element for Distance Protection
234
Load Blinding Setup
235
Delta Directional Element Setting Guidelines
236
Figure 99: Example Power System
237
Distance Protection Worked Example
237
Line Impedance Calculation
238
Zone 2 Phase and Ground Reach Settings
239
Load Avoidance
240
Figure 100: Apparent Impedances Seen by Distance Protection on a Teed Feeder
242
Teed Feeder Applications
242
Chapter 8 Carrier Aided Schemes
243
Chapter Overview
245
Introduction
246
Figure 101: Scheme Assignment
247
Carrier Aided Schemes Implementation
247
Default Carrier Aided Schemes
248
Aided Distance Scheme Logic
249
Figure 102: Aided Distance PUR Scheme
250
Permissive Over-Reach Scheme
250
Figure 103: Aided Distance por Scheme
252
Permissive Overreach Trip Reinforcement
252
Permissive Overreach Weak Infeed Features
253
Current Reversal Guard Logic
254
Figure 104: Example of Fault Current Reversal of Direction
254
Aided Distance Blocking Schemes
255
Aided Distance Unblocking Schemes
256
Figure 105: Aided Distance Blocking Scheme (BOP)
256
Figure 106: Aided Distance Send Logic
258
Figure 107: Carrier Aided Schemes Receive Logic
259
Figure 108: Aided Distance Tripping Logic
259
Figure 109: PUR Aided Tripping Logic
260
Figure 110: por Aided Tripping Logic
261
Figure 111: Aided Scheme Blocking 1 Tripping Logic
262
Figure 112: Aided Scheme Blocking 2 Tripping Logic
262
Aided DEF Scheme Logic
263
Zero Sequence Polarizing
264
Figure 113: Virtual Current Polarization
265
Negative Sequence Polarizing
265
Aided DEF Setting Guidelines
266
Figure 114: Directional Criteria for Residual Voltage Polarization
266
Aided DEF por Scheme
267
Figure 115: Aided DEF por Scheme
268
Aided DEF Logic Diagrams
269
Figure 116: Aided DEF Blocking Scheme
269
Figure 117: DEF Directional Signals
269
Figure 118: Aided DEF Send Logic
270
Figure 119: Carrier Aided Schemes Receive Logic
270
Figure 120: Aided DEF Tripping Logic
271
Figure 121: por Aided Tripping Logic
272
Figure 122: Aided Scheme Blocking 1 Tripping Logic
273
Figure 123: Aided Scheme Blocking 2 Tripping Logic
273
Aided Delta Scheme Logic
274
Figure 124: Aided Delta por Scheme
275
Figure 125: Aided Delta Blocking Scheme
276
Figure 126: Aided Delta Send Logic
277
Figure 127: Carrier Aided Schemes Receive Logic
277
Figure 128: Aided Delta Tripping Logic
278
Figure 129: por Aided Tripping Logic
279
Figure 130: Aided Scheme Blocking 1 Tripping Logic
280
Figure 131: Aided Scheme Blocking 2 Tripping Logic
280
Application Notes
281
Aided DEF por Scheme
282
Figure 132: Apparent Impedances Seen by Distance Protection on a Teed Feeder
283
Teed Feeder Applications
283
POR Schemes for Teed Feeders
284
Blocking Schemes for Teed Feeders
285
Chapter 9 Non-Aided Schemes
287
Figure 133: Problematic Fault Scenarios for PUR Scheme Application to Teed Feeders
285
Section 8
289
Default Chapter
289
Chapter Overview
289
Non-Aided Schemes
290
Basic Schemes
291
Figure 134: Zone Starting Logic
292
Figure 135: Zone Timer Logic
293
Figure 136: Zone Trip Logic
293
Basic Scheme Setting
294
Figure 137: Basic Time Stepped Distance Scheme
294
Figure 138: Trip on Close Logic
295
Trip on Close Schemes
295
Figure 139: Trip on Close Based on CNV Level Detectors
296
Switch on to Fault (SOTF)
296
Figure 140: SOTF Tripping
297
Figure 141: SOTF Tripping with CNV
297
Figure 142: TOR Tripping Logic for Appropriate Zones
298
Figure 143: TOR Tripping Logic with CNV
298
Trip on Reclose Mode
298
Figure 144: Zone 1 Extension Scheme
300
Figure 145: Zone 1 Extension Logic
300
Zone1 Extension Scheme
300
Figure 146: Loss of Load Accelerated Trip Scheme
301
Loss of Load Scheme
301
Figure 147: Loss of Load Logic
302
Chapter 10 Power Swing Functions
303
Chapter Overview
305
Figure 148: Power Transfer Related to Angular Difference between Two Generation Sources
306
Introduction to Power Swing Blocking
306
Power Swing Blocking
308
Figure 149: Phase Selector Timing for Power Swing Condition
309
Figure 150: Phase Selector Timing for Fault Condition
310
Figure 151: Phase Selector Timing for Fault During a Power Swing
310
Figure 152: Slow Power Swing Detection Characteristic
311
Detection of a Fault During a Power Swing
312
Power Swing Load Blinding Boundary
313
Figure 153: Load Blinder Boundary Conditions
314
Power Swing Blocking Logic
314
Figure 154: Power Swing Blocking Logic
315
Power Swing Blocking Setting Guidelines
315
Figure 155: Setting the Resistive Reaches
316
Figure 156: Reactive Reach Settings
317
PSB Timer Setting Guidelines
317
Figure 157: PSB Timer Setting Guidelines
318
Figure 158: out of Step Detection Characteristic
319
Out of Step Protection
319
Out of Step Protection Operataing Principle
320
Figure 159: out of Step Logic Diagram
321
Figure 160: OST Setting Determination for the Positive Sequence Resistive Component OST R5
323
Figure 161: OST R6Max Determination
324
Figure 162: Example of Timer Reset Due to Movs Operation
326
Chapter 11 Autoreclose
329
Section 9
331
Default Chapter
331
Chapter Overview
331
Introduction to Autoreclose
332
Autoreclose Implementation
333
Autoreclose Logic Inputs from External Sources
334
Reset Lockout Input
335
Autoreclose Operating Sequence
336
Figure 163: Autoreclose Sequence for a Transient Fault
336
Figure 164: Autoreclose Sequence for an Evolving or Permanent Fault
337
Figure 165: Autoreclose Sequence for an Evolving or Permanent Fault - Single-Phase Operation
337
Autoreclose System Map
338
Figure 166: Key to Logic Diagrams
339
Autoreclose System Map Diagrams
340
Autoreclose Internal Signals
345
Autoreclose DDB Signals
347
Logic Modules
353
Figure 172: CB State Monitor Logic Diagram (Module 1)
354
Figure 173: Circuit Breaker Open Logic Diagram (Module 3)
355
Figure 174: CB in Service Logic Diagram (Module 4)
355
Figure 175: Autoreclose OK Logic Diagram (Module 8)
356
Figure 176: Autoreclose Enable Logic Diagram (Module 5)
356
Single-Phase and Three-Phase Autoreclose
357
Figure 177: Autoreclose Modes Enable Logic Diagram (Module 9)
358
Figure 178: Force Three-Phase Trip Logic Diagram (Module 10)
358
Figure 179: Autoreclose Initiation Logic Diagram (Module 11)
360
Figure 180: Autoreclose Trip Test Logic Diagram (Module 12)
360
AR External Trip Initiation Logic Diagram
361
Figure 181: Autoreclose Initiation by External Trip or Evolving Conditions (Module 13)
361
Figure 182: Protection Reoperation and Evolving Fault Logic Diagram (Module 20)
362
Figure 183: Fault Memory Logic Diagram (Module 15)
362
Figure 184: Autoreclose in Progress Logic Diagram (Module 16)
363
Figure 185: Autoreclose Sequence Counter Logic Diagram (Module 18)
364
Figure 186: Single-Phase Autoreclose Cycle Selection Logic Diagram (Module 19)
364
Figure 187: Three-Phase Autoreclose Cycle Selection Logic Diagram (Module 21)
365
Figure 188: Dead Time Start Enable Logic Diagram (Module 22)
366
Figure 189: Single-Phase Dead Time Logic Diagram (Module 24)
367
Figure 190: Three-Phase Dead Time Logic Diagram (Module 25)
368
Figure 191: Circuit Breaker Autoclose Logic Diagram (Module 32)
369
Figure 192: Prepare Reclaim Initiation Logic Diagram (Module 34)
370
Figure 193: Reclaim Time Logic Diagram (Module 35)
370
Figure 194: Successful Autoreclose Signals Logic Diagram (Module 36)
371
Figure 195: Autoreclose Reset Successful Indication Logic Diagram (Module 37)
371
Figure 196: Circuit Breaker Healthy and System Check Timers Healthy Logic Diagram (Module 39)
372
Figure 197: Autoreclose Shot Counters Logic Diagram (Module 41)
373
Figure 198: CB Control Logic Diagram (Module 43)
374
Circuit Breaker Control
374
Figure 199: Circuit Breaker Trip Time Monitoring Logic Diagram (Module 53)
375
Figure 200: AR Lockout Logic Diagram (Module 55)
376
Figure 201: Reset Circuit Breaker Lockout Logic Diagram (Module 57)
377
Figure 202: Pole Discrepancy Logic Diagram (Module 62)
378
Figure 203: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
379
Figure 204: Check Synchronisation Monitor for CB Closure (Module 60)
380
Figure 205: Voltage Monitor for CB Closure (Module 59)
381
Figure 206: Three-Phase Autoreclose System Check Logic Diagram (Module 45)
383
Figure 207: CB Manual Close System Check Logic Diagram (Module 51)
384
Setting Guidelines
385
Reclaim Time Setting Guidelines
386
Chapter 12 CB Fail Protection
387
Section 10
389
Default Chapter
389
Chapter Overview
389
Circuit Breaker Fail Protection
390
Circuit Breaker Fail Implementation
391
Circuit Breaker Fail Logic
393
Circuit Breaker Fail Logic - Part 2
394
Circuit Breaker Fail Logic - Part 3
395
Circuit Breaker Fail Logic - Part 4
396
Application Notes
397
Figure 212: CB Fail Timing
398
Setting Guidelines (Undercurrent)
398
Chapter 13 Current Protection Functions
399
Chapter Overview
401
Phase Fault Overcurrent Protection
402
Figure 213: Phase Overcurrent Protection Logic Diagram
404
POC Logic
404
Negative Sequence Overcurrent Protection
405
Figure 214: Negative Phase Sequence Overcurrent Protection Logic Diagram
406
NPSOC Logic
406
Setting Guidelines (Directional Element)
407
Earth Fault Protection
408
Directional Element
409
Figure 215: IDG Characteristic
409
Negative Sequence Polarisation
410
Figure 216: Earth Fault Protection Logic Diagram
411
Sensitive Earth Fault Protection
413
Figure 217: EPATR B Characteristic Shown for TMS = 1.0
414
Figure 218: Sensitive Earth Fault Protection Logic Diagram
414
Application Notes
415
Figure 219: Current Distribution in an Insulated System with C Phase Fault
415
Figure 220: Phasor Diagrams for Insulated System with C Phase Fault
416
Setting Guidelines (Insulated Systems)
416
Figure 221: Positioning of Core Balance Current Transformers
417
Figure 222: High Impedance REF Principle
418
Figure 223: High Impedance REF Connection
419
Thermal Overload Protection
420
Figure 224: Thermal Overload Protection Logic Diagram
421
Figure 225: Spreadsheet Calculation for Dual Time Constant Thermal Characteristic
422
Figure 226: Dual Time Constant Thermal Characteristic
422
Setting Guidelines for Single Time Constant Characteristic
423
Broken Conductor Protection
425
Transient Earth Fault Detection
427
Figure 227: Broken Conductor Logic
425
Transient Earth Fault Detection Implementation
428
Figure 228: Transient Earth Fault Logic Overview
429
Figure 229: Fault Type Detector Logic
430
Figure 230: Direction Detector Logic - Standard Mode
430
Figure 231: TEFD Output Alarm Logic
430
Chapter 14 Voltage Protection Functions
431
Chapter Overview
433
Undervoltage Protection
434
Figure 232: Undervoltage - Single and Three Phase Tripping Mode (Single Stage)
435
Undervoltage Protection Logic
435
Application Notes
436
Overvoltage Protection
437
Figure 233: Overvoltage - Single and Three Phase Tripping Mode (Single Stage)
438
Overvoltage Protection Logic
438
Application Notes
439
Compensated Overvoltage
440
Residual Overvoltage Protection
441
Figure 234: Residual Overvoltage Logic
442
Figure 235: Residual Voltage for a Solidly Earthed System
443
Calculation for Impedance Earthed Systems
443
Figure 236: Residual Voltage for an Impedance Earthed System
444
Setting Guidelines
444
Chapter 15 Frequency Protection Functions
445
Chapter Overview
447
Frequency Protection
448
Figure 237: Underfrequency Logic (Single Stage)
449
Underfrequency Protection Logic
449
Figure 238: Overfrequency Logic (Single Stage)
450
Overfrequency Protection Logic
450
Figure 239: Rate of Change of Frequency Logic (Single Stage)
451
Independent R.O.C.O.F Protection
451
Chapter 16 Current Transformer Requirements
453
Chapter Overview
455
Recommended CT Classes
456
Current Differential Requirements
457
Distance Protection Requirements
458
Determining Vk for IEEE C-Class CT
459
Worked Examples
460
Calculation of Total Impedance up to Remote Busbar
461
Calculation of Vk for Distance Zone 1 Close-Up Fault
462
Chapter 17 Monitoring and Control
463
Chapter Overview
465
Event Records
466
Opto-Input Events
467
Fault Record Events
468
Figure 240: Fault Recorder Stop Conditions
468
Security Events
469
Disturbance Recorder
470
Measurements
471
CB Condition Monitoring
472
Figure 241: Broken Current Accumulator Logic Diagram
473
Figure 242: CB Trip Counter Logic Diagram
473
Figure 243: Operating Time Accumulator
474
Figure 244: Excessive Fault Frequency Logic Diagram
474
Figure 245: Reset Lockout Alarm Logic Diagram
475
Figure 246: CB Condition Monitoring Logic Diagram
476
Figure 247: Reset Circuit Breaker Lockout Logic Diagram (Module 57)
477
Setting the Thresholds for the Number of Operations
478
CB State Monitoring
479
Figure 248: CB State Monitor Logic Diagram (Module 1)
480
Circuit Breaker Control
481
Figure 249: Hotkey Menu Navigation
482
CB Control Using the Hotkeys
482
CB Control Using the Opto-Inputs
483
Figure 250: Default Function Key PSL
483
CB Healthy Check
484
Figure 251: Remote Control of Circuit Breaker
484
Figure 252: CB Control Logic Diagram (Module 43)
485
Figure 253: Pole Dead Logic
486
Pole Dead Function
486
System Checks
487
Voltage Monitoring
488
Figure 254: Check Synchronisation Vector Diagram
489
Figure 255: Voltage Monitor for CB Closure (Module 59)
490
Figure 256: Check Synchronisation Monitor for CB Closure (Module 60)
491
Figure 257: System Check PSL
492
Chapter 18 Supervision
495
Chapter Overview
497
Current Differential Supervision
498
Figure 258: Current Differential Starter Supervision Logic
500
Figure 259: Current Differential Function Start Logic
501
Communications Asymmetry Supervision
502
Figure 260: Switched Communication Path Supervision
502
Figure 261: Communication Asymmetry Supervision
503
GPS Synchronisation Supervision
503
Propogation Delay Management
504
Voltage Transformer Supervision
506
VTS Implementation
507
VTS Logic
509
Figure 262: VTS Logic
510
Current Transformer Supervision
511
Figure 263: Differential CTS
512
Differential CTS Logic
512
Figure 264: Standard CTS
513
Standard CTS Logic
513
Differential CTS Setting Guidelines
514
Trip Circuit Supervision
515
Figure 266
516
Resistor Values
517
Resistor Values
518
Chapter 19 Digital I/O and PSL Configuration
519
Chapter Overview
521
Configuring Digital Inputs and Outputs
522
Figure 271: Scheme Logic Interfaces
523
PSL Editor
524
Configuring the Opto-Inputs
525
Assigning the Output Relays
526
Figure 272: Trip LED Logic
527
Fixed Function Leds
527
Configuring Programmable Leds
528
Function Keys
530
Control Inputs
531
Chapter 20 Fibre Teleprotection
533
Chapter Overview
535
Protection Signalling Introduction
536
Transmission Media and Interference
537
Fibre Teleprotection Implementation
538
Figure 273: Fibre Teleprotection Connections for a Three-Terminal Scheme
539
Setting up IM64
540
Three-Terminal IM64 Operation
541
Physical Connection
542
Figure 274: Interfacing to PCM Multiplexers
544
Communications Supervision
545
Figure 275: IM64 Channel Fail and Scheme Fail Logic
547
Figure 276: IM64 General Alarm Signals Logic
547
Figure 277: IM64 Communications Mode and IEEE C37.94 Alarm Signals
548
Application Notes
549
Figure 278: IM64 Two-Terminal Scheme Extended Supervision
550
Figure 279: IM64 Three-Terminal Scheme Extended Supervision
550
Chapter 21 Electrical Teleprotection
553
Chapter Overview
555
Introduction
556
Teleprotection Scheme Principles
557
Implementation
558
Configuration
559
Figure 280: Example Assignment of Intermicom Signals Within the PSL
560
Connecting to Electrical Intermicom
561
Figure 281: Direct Connection
561
Figure 282: Indirect Connection Using Modems
561
Application Notes
562
Chapter 22 Communications
565
Chapter Overview
567
Communication Interfaces
568
Serial Communication
569
EIA(RS)485 Biasing Requirements
570
Figure 283: RS485 Biasing Circuit
570
Figure 284: Remote Communication Using K-Bus
571
Standard Ethernet Communication
572
Redundant Ethernet Communication
573
Figure 285: IED Attached to Separate Lans
574
Parallel Redundancy Protocol
574
Figure 286: HSR Multicast Topology
575
High-Availability Seamless Redundancy (HSR)
575
Figure 287: HSR Unicast Topology
576
Figure 288: HSR Application in the Substation
577
Figure 289: IED Attached to Redundant Ethernet Star or Ring Circuit
577
Rapid Spanning Tree Protocol
577
Figure 290: IED, Bay Computer and Ethernet Switch with Self Healing Ring Facilities
578
Figure 291: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches
578
Self Healing Protocol
578
Dual Homing Protocol
579
Figure 292: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches
579
Figure 293: Dual Homing Mechanism
580
Configuring IP Addresses
581
Figure 294: Application of Dual Homing Star at Substation Level
581
Configuring the IED IP Address
582
Figure 295: IED and REB IP Address Configuration
582
PRP/HSR Configurator
585
Figure 296: Connection Using (A) an Ethernet Switch and (B) a Media Converter
586
Installing the Configurator
586
PRP/HSR Device Identification
587
HSR Configuration
588
End of Session
589
Figure 297: Connection Using (A) an Ethernet Switch and (B) a Media Converter
590
Installing the Configurator
590
RSTP IP Address Configuration
591
End of Session
592
Installation
593
Setup
594
Mirroring Function
595
Simple Network Management Protocol (SNMP)
596
Redundant Ethernet Board MIB Structure
597
Accessing the MIB
601
Data Protocols
603
Courier Database
604
Disturbance Record Extraction
606
Courier Configuration
607
Iec 60870-5-103
608
Initialisation
609
Test Mode
610
Physical Connection and Link Layer
612
Figure 298: Control Input Behaviour
613
Object 20 Binary Counters
613
Object 40 Analogue Output
614
DNP3 Configuration
622
Iec 61850
623
Benefits of IEC 61850
624
Figure 299: Data Model Layers in IEC61850
625
IEC 61850 in Micom Ieds
625
IEC 61850 Data Model Implementation
626
Ethernet Functionality
627
IEC 61850 Edition 2
628
Figure 300: Edition 2 System - Backward Compatibility
629
Figure 301: Edition 1 System - Forward Compatibility Issues
629
Figure 302: Example of Standby IED
630
Figure 303: Standby IED Activation Process
631
Read Only Mode
632
IEC 61850 Protocol Blocking
633
Figure 304: GPS Satellite Timing Signal
634
Time Synchronisation
634
IRIG-B Implementation
635
Figure 305: Timing Error Using Ring or Line Topology
636
PTP Domains
636
Chapter 23 Cyber-Security
637
Overview
639
The Need for Cyber-Security
640
Standards
641
Cip 002
642
Cip 007
643
Cyber-Security Implementation
645
Figure 306: Default Display Navigation
646
Four-Level Access
646
Blank Passwords
647
Access Level Ddbs
648
Password Blocking
649
Password Recovery
650
Password Encryption
651
Security Events Management
652
Logging out
654
Chapter 24 Installation
655
Chapter Overview
657
Handling the Goods
658
Figure 307: Location of Battery Isolation Strip
659
Mounting the Device
659
Figure 308: Rack Mounting of Products
660
Cables and Connectors
662
Figure 309: Terminal Block Types
662
Power Supply Connections
663
Voltage Transformer Connections
664
Ethernet Metallic Connections
665
Figure 310: 40TE Case Dimensions
666
Figure 311: 60TE Case Dimensions
667
Figure 312: 80TE Case Dimensions
668
Chapter 25 Commissioning Instructions
669
Chapter Overview
671
General Guidelines
672
Commissioning Test Menu
673
Test Mode Cell
674
Static Test Mode
675
IM64 Test Pattern
676
Commissioning Equipment
677
Advisory Test Equipment
678
Product Checks
679
Visual Inspection
680
Watchdog Contacts
681
Test LCD
682
Test Leds
683
Figure 313: RP1 Physical Connection
684
Test Output Relays
684
Figure 314: Remote Communication Using K-Bus
685
Test Serial Communication Port RP2
685
Test Ethernet Communication
686
Test Voltage Inputs
687
Figure 315: Intermicom Loopback Testing
688
Electrical Intermicom Communication Loopback
688
Intermicom Command Bits
689
Intermicom 64 Communication
690
Setting up the Loopback
691
GPS Synchronisation
692
Setting Checks
693
IEC 61850 Edition 2 Testing
695
Simulated Input Behaviour
696
Test Procedure for Real Values
697
Test Procedure for Simulated Values - with Plant
698
Contact Test
699
Current Differential Protection
700
Upper Slope
701
Distance Protection
703
Zone 1 Reach Check
704
Zone 3 Reach Check
705
Load Blinder
706
Time Delay Settings
707
Scheme Trip Test for Zone 1 Extension
708
Signal Send Test for Permissive Schemes
709
Delta Directional Comparison
710
Operation and Contact Assignment
711
Delta Protection Scheme Testing
712
DEF Aided Schemes
713
Preliminaries
714
Scheme Testing
715
Out of Step Protection
716
Predictive OST Setting
717
Protection Timing Checks
718
Performing the Test
719
System Check and Check Synchronism
720
Check Trip and Autoreclose Cycle
721
End-To-End Communication Tests
722
Restoring C37.94 Fibre Connections
723
End-To-End Scheme Tests
725
Onload Checks
727
Measure Capacitive Charging Current
728
Final Checks
729
Commmissioning the P59X
730
P59X Leds
731
Loopback Test
732
Chapter 26 Maintenance and Troubleshooting
733
Chapter Overview
735
Maintenance
736
Replacing the Device
737
Repairing the Device
738
Replacing Pcbs
739
Replacement of Communications Boards
740
Replacement of the Input Module
741
Replacement of the I/O Boards
742
Post Modification Tests
743
Troubleshooting
744
Out of Service LED on at Power-Up
745
Error Code During Operation
746
Incorrect Analogue Signals
747
IEEE C37.94 Fail
748
Chapter 27 Technical Specifications
751
Chapter Overview
753
Interfaces
754
Rear Serial Port 2
755
Rear Ethernet Port Copper
756
Base FX Transmitter Characteristics
757
Protection Functions
758
Distance Protection
759
Out of Step Protection
760
Transient Overreach and Overshoot
761
Sensitive Earth Fault Protection
762
NPSOC Directional Parameters
763
Monitoring, Control and Supervision
764
PSL Timers
765
Measurements and Recording
766
Ratings
767
Nominal Burden
768
Battery Backup
769
Input / Output Connections
770
High Break Output Contacts
771
Mechanical Specifications
772
Type Tests
773
Environmental Conditions
774
Electromagnetic Compatibility
775
Surge Immunity Test
776
Magnetic Field Immunity
777
Regulatory Compliance
778
4
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GE MiCOM P40 Agile Specifications
General
Brand
GE
Model
MiCOM P40 Agile
Category
Control Unit
Language
English
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