GDM-906X Series User Manual
334
STATus Report Commands
STATus:OPERation:CONDition?
Returns the total number of the Operation Condition register.
Return parameter: <NR1>, Ex: +4096
●A condition register continuously monitors the state of the instrument.
Condition register bits are updated in real time; they are neither latched nor
buffered.
This register is read-only; bits are not cleared when read.
STATus:OPERation:ENABle
Sets bits in the Operation Enable register.
Parameter: <NR1> (0~32767)
Example: STAT:OPER:ENAB 10
Sets the bit1 and bit3 in Operation Enable register, 10 = 2
1
+ 2
3
.
●The selected bits are then reported to the Status Byte. An enable register
defines which bits in the event register will be reported to the Status Byte
register group. You can write to or read from an enable register.
●A STATus:PRESet clears all bits in the enable register.
●The *PSC command controls whether the enable register is cleared at
power on.
STATus:OPERation:ENABle?
Returns the total number of the Operation Enable register.
Return parameter: <NR1>, Ex: +256
STATus:OPERation[:EVENt]?
Returns the total number of the Operation Event register.
Return parameter: <NR1>, Ex: +786
●An event register is a read-only register that latches events from the
condition register. While an event bit is set, subsequent events
corresponding to that bit are ignored.
●Once a bit is set, it remains set until cleared by reading the event register
or by sending *CLS (clear status).
STATus:PRESet
Clears the Operation Enable register and Questionable Enable register.
Example: STAT:PRES
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