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Intel 8XC251SA User Manual
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A-5
INSTRUCTION SET REFERENCE
T
able A-7. New Ins
tructions for the
M
CS
®
251
Architecture
Bin.
A5
x
8A
5
x
9A
5
x
AA
5
x
BA
5
x
CA
5
x
DA
5
x
EA
5
x
F
Src.
x
8
x
9
x
A
x
B
x
C
x
D
x
E
x
F
0
JSL
E
rel
MOV
Rm,@WRj+dis
MOVZ
WRj,Rm
INC R,#
short (
1)
MOV reg,
ind
SRA
reg
1
JSG
rel
MOV
@WRj+dis,Rm
MOVS
WRj,Rm
DEC R,#short (1)
MOV ind,reg
SRL
reg
2J
L
E
rel
MOV
Rm,@DRk+dis
ADD
Rm,Rm
ADD
WRj,WRj
ADD
reg,op
2 (2)
ADD
DRk,DRk
3J
G
rel
MOV
@DRk+dis,Rm
SLL
reg
4
JSL
rel
MOV
WRj,@WRj+dis
ORL
Rm,Rm
ORL
WRj,WRj
ORL
reg,op
2
(2)
5
JSG
E
rel
MOV
@WRj+dis,WRj
ANL
Rm,Rm
ANL
WRj,WRj
ANL
reg,op
2
(2)
6J
E
rel
MOV
WRj,@DRk+dis
XRL
Rm,Rm
XRL
WRj,WRj
XRL
reg,op
2
(2)
7
JNE
rel
MOV
@DRk+dis,WRj
MOV
op1,r
eg (
2)
MOV
Rm,Rm
MOV
WRj,WRj
MOV
reg,op
2
(2)
MOV
DRk,DRk
8
LJMP @WRj
EJMP @DRk
EJMP
addr
24
DIV
Rm,Rm
DIV
WRj,WRj
9
LCALL
@WRj
ECALL @DRk
ECALL
addr
24
SUB
Rm,Rm
SUB
WRj,WRj
SUB
reg,op
2
(2)
SUB
DRk,DRk
A
Bit
Instruc
tions (3)
ERET
MUL
Rm,Rm
MUL
WRj,WRj
B
TRAP
CMP
Rm,Rm
CMP
WRj,WRj
CMP
reg,op
2
(2)
CMP
DRk,DRk
C
PUSH op1 (4)
MOV DRk,PC
D
POP
op1
(4)
E
F
NOTES
:
1.
R = Rm/WRj/DRk.
2.
op1, op2 are defined in T
able A-8.
3.
See T
ables A-
10 and A-1
1.
4.
See T
able A-12.
256
258
Table of Contents
Default Chapter
5
Table of Contents
5
Chapter 1 Guide to this Manual
19
Manual Contents
21
Notational Conventions and Terminology
23
Related Documents
25
Data Sheet
26
Application Notes
26
Application Support Services
27
World Wide Web
27
Compuserve Forums
27
Faxback Service
28
Bulletin Board System (BBS)
28
Chapter 2 Architectural Overview
31
8Xc251Sa, Sb, Sp, Sq Architecture
35
Mcs 251 Microcontroller Core
36
Cpu
37
Clock and Reset Unit
38
Interrupt Handler
39
On-Chip Code Memory
39
On-Chip RAM
39
On-Chip Peripherals
39
Timer/Counters and Watchdog Timer
39
Programmable Counter Array (PCA)
40
Serial I/O Port
40
Chapter 3 Address Spaces
41
Compatibility with the MCS® 51 Architecture
44
8Xc251Sa, Sb, Sp, Sq Memory Space
47
On-Chip General-Purpose Data RAM
50
On-Chip Code Memory (83C251SA, SB, SP, SQ/87C251SA, SB, SP, SQ)
50
Accessing On-Chip Code Memory in Region 00
51
External Memory
52
8Xc251Sa, Sb, Sp, Sq Register File
52
Byte, Word, and Dword Registers
55
Dedicated Registers
55
Accumulator and B Register
55
Extended Data Pointer, DPX
57
Extended Stack Pointer, SPX
57
Special Function Registers (Sfrs)
58
Chapter 4 Device Configuration
63
Configuration Overview
65
Device Configuration
65
The Configuration Bits
68
Configuration Byte Location Selector (Ucon)
69
Configuring the External Memory Interface
72
Page Mode and Nonpage Mode (PAGE#)
72
Configuration Bits RD1:0
73
RD1:0 = 00 (18 External Address Bits)
73
RD1:0 = 01 (17 External Address Bits)
73
RD1:0 = 10 (16 External Address Bits)
76
RD1:0 = 11 (Compatible with MCS 51 Microcontrollers)
76
Wait State Configuration Bits
76
Configuration Bits WSA1:0#, WSB1
76
Configuration Bit WSB
76
Configuration Bit XALE
77
Opcode Configurations (Src)
77
Selecting Binary Mode or Source Mode
78
Mapping On-Chip Code Memory to Data Memory (Emap#)
80
Interrupt Mode (Intr)
80
Chapter 5 Programming
81
Source Mode or Binary Mode Opcodes
83
Data Types
84
Order of Byte Storage for Words and Double Words
84
Register Notation
84
Address Notation
84
Addressing Modes
86
Data Instructions
86
Data Addressing Modes
86
Register Addressing
87
Immediate
87
Direct
87
Indirect
88
Displacement
90
Arithmetic Instructions
90
Logical Instructions
91
Data Transfer Instructions
92
Bit Instructions
93
Bit Addressing
93
Control Instructions
94
Addressing Modes for Control Instructions
95
Conditional Jumps
96
Unconditional Jumps
97
Calls and Returns
97
Program Status Words
98
Chapter 6 Interrupt System
103
Overview
105
8Xc251Sa, Sb, Sp, Sq Interrupt Sources
107
External Interrupts
107
Timer Interrupts
108
Programmable Counter Array (Pca) Interrupt
109
Serial Port Interrupt
109
Interrupt Enable
109
Interrupt Priorities
111
Interrupt Processing
113
Minimum Fixed Interrupt Time
114
Variable Interrupt Parameters
114
Response Time Variables
114
Computation of Worst-Case Latency with Variables
116
Latency Calculations
117
Blocking Conditions
118
Interrupt Vector Cycle
118
Isrs in Process
119
Chapter 7 Input/Output Ports
121
Input/Output Port Overview
123
I/O Configurations
124
Port 1 and Port 3
124
Port 0 and Port 2
124
Read-Modify-Write Instructions
127
Quasi-Bidirectional Port Operation
128
Port Loading
129
External Memory Access
129
Chapter 8 Timer/Counters and Watchdog Timer
133
Timer/Counter Overview
135
Timer/Counter Operation
135
Timer 0
137
Mode 0 (13-Bit Timer)
138
Mode 1 (16-Bit Timer)
138
Mode 2 (8-Bit Timer with Auto-Reload)
139
Mode 3 (Two 8-Bit Timers)
139
Timer 1
139
Mode 0 (13-Bit Timer)
143
Mode 1 (16-Bit Timer)
143
Mode 2 (8-Bit Timer with Auto-Reload)
143
Mode 3 (Halt)
143
Timer 0/1 Applications
143
Auto-Load Setup Example
143
Pulse Width Measurements
144
Timer 2
144
Capture Mode
145
Auto-Reload Mode
146
Up Counter Operation
146
Up/Down Counter Operation
147
Baud Rate Generator Mode
148
Clock-Out Mode
148
Watchdog Timer
150
Description
150
Using the WDT
152
WDT During Idle Mode
152
WDT During Powerdown
152
Chapter 9 Programmable Counter Array
153
Pca Description
155
Alternate Port Usage
156
Pca Timer/Counter
156
Pca Compare/Capture Modules
159
16-Bit Capture Mode
159
Compare Modes
161
16-Bit Software Timer Mode
161
High-Speed Output Mode
162
PCA Watchdog Timer Mode
163
Pulse Width Modulation Mode
165
Chapter 10 Serial I/O Port
171
Overview
173
Modes of Operation
176
Synchronous Mode (Mode 0)
176
Transmission (Mode 0)
176
Reception (Mode 0)
177
Asynchronous Modes (Modes 1, 2, and 3)
178
Transmission (Modes 1, 2, 3)
178
Reception (Modes 1, 2, 3)
178
Framing Bit Error Detection (Modes 1, 2, and 3)
179
Multiprocessor Communication (Modes 2 and 3)
179
Automatic Address Recognition
179
Given Address
180
Broadcast Address
181
Reset Addresses
182
Baud Rates
182
Baud Rate for Mode 0
182
Baud Rates for Mode 2
182
Baud Rates for Modes 1 and 3
182
Timer 1 Generated Baud Rates (Modes 1 and 3)
183
Selecting Timer 1 as the Baud Rate Generator
183
Timer 2 Generated Baud Rates (Modes 1 and 3)
184
Selecting Timer 2 as the Baud Rate Generator
184
Chapter 11 Minimum Hardware Setup
187
Electrical Environment
190
Power and Ground Pins
190
Unused Pins
190
Noise Considerations
190
Clock Sources
191
On-Chip Oscillator (Crystal)
191
On-Chip Oscillator (Ceramic Resonator)
192
External Clock
192
Reset
193
Externally Initiated Resets
194
WDT Initiated Resets
194
Reset Operation
194
Power-On Reset
195
Chapter 12 Special Operating Modes
197
General
199
Power Control Register
199
Serial I/O Control Bits
199
Power off Flag
199
Idle Mode
202
Entering Idle Mode
202
Exiting Idle Mode
203
Powerdown Mode
203
Entering Powerdown Mode
204
Exiting Powerdown Mode
204
On-Circuit Emulation (Once) Mode
205
Entering ONCE Mode
205
Exiting ONCE Mode
205
Chapter 13 External Memory Interface
207
Overview
209
External Bus Cycles
211
Bus Cycle Definitions
211
Page Mode Bus Cycles
213
Wait States
216
External Bus Cycles with Configurable Wait States
216
Extending RD#/WR#/PSEN
216
Extending ALE
218
External Bus Cycles with Real-Time Wait States
218
Real-Time WAIT# Enable (RTWE)
220
Real-Time WAIT CLOCK Enable (RTWCE)
220
Real-Time Wait State Bus Cycle Diagrams
220
Port 0 and Port 2 Status
224
Port 0 and Port 2 Pin Status in Nonpage Mode
224
Port 0 and Port 2 Pin Status in
225
External Memory Design Examples
226
Example 1: RD1:0 = 00, 18-Bit Bus, External Flash and RAM
226
Example 2: RD1:0 = 01, 17-Bit Bus, External Flash and RAM
228
Example 3: RD1:0 = 01, 17-Bit Bus, External RAM
230
Example 4: RD1:0 = 10, 16-Bit Bus, External RAM
232
Example 5: RD1:0 = 11, 16-Bit Bus, External EPROM and RAM
234
An Application Requiring Fast Access to the Stack
234
An Application Requiring Fast Access to Data
234
Example 6: RD1:0 = 11, 16-Bit Bus, External EPROM and RAM
237
Example 7: RD1:0 = 01, 17-Bit Bus, External Flash
238
Chapter 14
241
Programming and Verifying
241
Nonvolatile Memory
241
General
241
Programming Considerations for On-Chip Code Memory
242
EPROM Devices
243
Programming and Verifying Modes
243
General Setup
243
Programming Algorithm
245
Verify Algorithm
246
Programmable Functions
246
On-Chip Code Memory
247
Configuration Bytes
247
Lock Bit System
247
Encryption Array
248
Signature Bytes
248
Verifying the 83C251Sa, Sb, Sp, Sq (Rom)
249
Appendix A Instruction Set Reference
251
Instruction Set Summary
263
Execution Times for Instructions that Access the Port Sfrs
263
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Intel 8XC251SA Specifications
General
Brand
Intel
Model
8XC251SA
Category
Microcontrollers
Language
English
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