Intel 8XC251SA - Page 451

INDEX
Index-3
ECI, 7-1
EJMP instruction, 5-15, A-24
EMAP# bit, 3-9, 4-16
Encryption, 14-2
Encryption array
key bytes, 14-8
programming, 14-1, 14-8
setup for programming, 14-4–14-5
ERET instruction, 5-15, A-24
Escape prefix (A5H), 4-14
Extended stack pointer, See SPX
Extending ALE, A-1
extending ALE, A-11
External address lines
number of, 4-9
External bus
inactive, 13-3
pin status, 13-16, 13-17
structure in page mode, nonpage mode, 13-5
External bus cycles, 13-3
definitions, 13-3
extended ALE wait state, 13-10
extended RD#/WR#/PSEN# wait state, 13-8
nonpage mode, 13-4, 13-5
page mode, 13-5–13-7
page-hit vs page-miss, 13-5
External code memory
example, 13-20, 13-30
idle mode, 12-4
powerdown mode, 12-5
External memory, 3-10
design examples, 13-18–13-30
MCS 51 architecture, 3-2, 3-4, 3-5
External memory interface
configuring, 4-8–4-16
signals, 13-1
External RAM
example, 13-26
exiting idle mode, 12-5
F
F0 flag, 5-18, C-20
FaxBack service, 1-7, 1-8
Flash memory
example, 13-18, 13-20, 13-30
G
Given address, See Serial I/O port
Ground bounce, 11-2
H
Hardware
application notes, 1-6
Help desk, 1-7
I
I/O ports, 7-1–7-9
external memory access, 7-7, 7-8
latches, 7-2
loading, 7-7
pullups, 7-6
quasi-bidirectional, 7-6
SFRs, 3-18
See also Ports 0–3
Idle mode, 2-4, 12-1, 12-4–12-5
entering, 12-4
exiting, 11-6, 12-5
external bus, 13-3
IE, 6-3, 6-5
IE0, 3-17, 3-18, 6-6, 6-14, 10-11, C-2, C-3, C-14
Immediate addressing, 5-4
INC instruction, 5-8, A-16
Indirect addressing, 5-4
in control instructions, 5-13
in data instructions, 5-6
Instruction set
MCS 251 architecture, 5-1
MCS 51 architecture, 5-1
Instructions
arithmetic, 5-8
bit, 5-11
data, 5-4
data transfer, 5-10
logical, 5-9
INT1:0#, 6-1, 7-1, 8-1, 8-3
pulse width measurements, 8-10
Interrupt request, 6-1
cleared by hardware, 6-4
Interrupt service routine
exiting idle mode, 12-5
exiting powerdown mode, 12-6
Interrupts, 6-1–6-15
blocking conditions, 6-14