Intel E810-CQDA2T - Page 75

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Intel
®
Ethernet Network Adapter E810-CQDA2T
User Guide
• Intel recommends disabling UART1 and UART2 interfaces on the GNSS receiver. To do that, use:
1. Disable UART1 in RAM, and Flash:
# ubxtool -v 1 -w 1 -P 29.20 -z CFG-UART1-ENABLED,0,5
Or open two terminals and run:
# cat /dev/gnssX //Terminal 1
# echo -ne
"\xb5\x62\x06\x8a\x09\x00\x00\x05\x00\x00\x05\x00\x52\x10\x00\x05\x80" > /dev/
gnssX //Terminal 2
2. Disable UART2 in RAM, and Flash:
# ubxtool -v 3 -w 1 -P 29.20 -z CFG-UART2-ENABLED,0,5
Or open two terminals and run:
# cat /dev/gnssX //Terminal 1
# echo -ne
"\xb5\x62\x06\x8a\x09\x00\x00\x05\x00\x00\x05\x00\x53\x10\x00\x06\x83" > /dev/
gnssX //Terminal 2
• In some cases, when GNSS loses the antenna reference, the GNSS might output for couple of
seconds the 1PPS signal and NMEA messages. To more rapidly disqualify the 1PPS and NMEA
messages, increase the filtering of GNSS receiver with ubxtool command:
# ubxtool -P 29.20 -v 1 -w 1 -z CFG-NAVSPG-OUTFIL_TACC,10,5
Or open two terminals and run:
# cat /dev/gnssX //Terminal 1
#echo -ne
"\xb5\x62\x06\x8a\x0a\x00\x00\x05\x00\x00\xb4\x00\x11\x30\x0a\x00\x9e\x1b" >
/dev/gnssX //Terminal2
• Because of a known driver limitation, before enabling the periodic outputs to the DPLL, make sure
that your PHC is synchronized (wait for stable ptp4l connection with dual digit offset). If you need
to do a jump on the PHC clock (like restarting ptp4l), you must to disable 1PPS and 10 MHz signal
to DPLL. If the clock jumped, the periodic outputs to the DPLL might not ever show a “valid” state in
the CGU Linux interface. To restore correct operation of DPLL, reload the driver:
# rmmod ice; modprobe ice