Intel i960 - Page 251

i960 Processor Compiler User's Guide
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7
Example 2: sf1.c (Complex)
The following example refers to the short C program shown in
Example 7-2. The asm containing the
sf1 instruction is shown in bold.
Example 7-2 sf1.c (Complex)
/*
* Changes interrupt mask, and returns old interrupt mask
* for i960 CA microprocessor. Illustrates & constraint.
*/
int change_interrupt_mask(int new_mask)
{
int old_mask;
asm volatile ("mov sf1,%0; mov %1,sf1":
"=&d" (old_mask) : "dI" (new_mask));
return old_mask;
}
Consider the line containing the asm:
asm volatile ("mov sf1,%0; mov %1,sf1":
"=&d" (old_mask) : "dI" (new_mask));
• "mov sf1,%0; mov %1,sf1" is the asm-template . The
asm-template actually contains two mov instructions. The first
writes the contents of register
sf1 onto operand 0 (old_mask) and the
second writes operand 1 (
new_mask) into register sf1.
•
"=&d" (old_mask) is the only output-spec . It is the first operand
(operand 0). The
"=&d" is the constraint . The = says that this
operand must be assignable. The
& tells gcc960 not to allocate this
output in the same register as an input operand. This is necessary
because the first
mov creates output before the second mov has used its
input. The
d indicates that this operand must go in a word register. If
old_mask is not a word register, the compiler generates code
following the asm to copy the word register it chose for this output
operand into
old_mask.