i960 Processor Compiler User's Guide
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11
Instruction Selection and Sequencing
In addition to other optimizations, the compiler can reduce or eliminate
instructions that have become redundant or useless. The compiler can also
eliminate less efficient instructions or replace them with instruction
sequences and addressing modes that take advantage of i960 processor
features. These instruction optimizations include:
• code compression
• code scheduling
• specialized instruction selection
Code Compression
The i960 architecture provides complex addressing-mode instructions that
enable denser code generation. By default, the compiler tries to pick
addressing modes to maximize run-time performance, generally using a
mix of complex and simple addressing modes. You can control this
optimization with
#pragma compress, as described in Chapter 7.
Code Scheduling
In code scheduling, the compiler modifies the sequence of instructions to
increase parallel execution. Although the effect of the code does not
change, code scheduling can often improve code performance.
Since different members of the i960 family of processors provide varying
levels of hardware parallelism, the compiler orders the instructions
differently according to the specific processor for which code is being
generated.
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