Datasheet 11
Features Summary
1.2 Processor Feature Details
• Two execution cores
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 512-KB shared instruction/data second-level cache (L2), 256-KB for each core
• Up to 3-MB shared instruction/data third-level cache (L3), shared among all cores
1.2.1 Supported Technologies
• Intel® 64 architecture
• Execute Disable Bit
• Processor Context Identifier (PCID) (U5400 processor only)
Note: Please refer to the Intel® Pentium® P6000 and U5000 Mobile Processor Series
Specification Update for feature support details
1.3 Interfaces
1.3.1 System Memory Support
• One or two channels of DDR3 memory with a maximum of one SO-DIMM per
channel
• Single- and dual-channel memory organization modes
• Data burst length of eight for all memory organization modes
• Memory DDR3 data transfer rates of 800 MT/s (SV/ULV) and 1066 MT/s (SV)
• 64-bit wide channels
• DDR3 I/O Voltage of 1.5 V
• Non-ECC, unbuffered DDR3 SO-DIMMs only
• Theoretical maximum memory bandwidth of:
— 12.8 GB/s in dual-channel mode assuming DDR3 800 MT/s
• 1-Gb, and 2-Gb DDR3 DRAM technologies are supported for x8 and x16 devices.
• Using 2-Gb device technologies, the largest memory capacity possible is 8 GB,
assuming dual-channel mode with two x8, double-sided, un-buffered, non-ECC,
SO-DIMM memory configuration.
• Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 Bank
Devices)
• Memory organizations:
— Single-channel modes
— Dual-channel modes - Intel® Flex Memory Technology:
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